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					CSL718 : Pipelined Processors


       Types of Pipelines
       Types of Hazards
         16th Jan, 2006

         Anshul Kumar, CSE IITD
   Types of Pipelined processors
• Degree of overlap
  – Serial, Overlapped, Pipelined, Super-pipelined
• Depth
  – Shallow, Deep
• Structure
  – Linear, Non - linear
• Scheduling of operations
  – Static, Dynamic


  Anshul Kumar, CSE IITD                             slide 2
Degree of overlap         Depth
     Serial                Shallow




    Overlapped


                            Deep

      Pipelined




 Anshul Kumar, CSE IITD              slide 3
             Pipeline Structure

  Linear
                              A          B         C
 Pipeline




Non-linear
                              A          B         C
 Pipeline


                         Sequence: A, B, C, B, C, A, C, A

Anshul Kumar, CSE IITD                                      slide 4
Scheduling/timing alternatives

• Static
   – same sequence of stages for all instructions
   – all actions in order
   – if one instruction stalls, all subsequent
     instructions are delayed
• Dynamic
   – above conditions are relaxed
   – higher throughput is achieved


Anshul Kumar, CSE IITD                              slide 5
           Dynamic Scheduling
• type 1 : beginnings (decode) and endings
  (put away) in order
• type 2 : only beginnings in order
• type 3 : no order restrictions except
  dependencies
• type 1 extended : beginnings in order,
  references that effect memory state are in
  order
     [note that a memory reference may lead to page
     fault]
Anshul Kumar, CSE IITD                          slide 6
            Pipelining and CPI
                   Type           CPI
                  Serial         5–6
              Overlapped           3
         Pipelined (static)     1.5 – 2
       Pipelined (dynamic)      1.2 – 1.5
   Multiple instruction issue    < 1.0

Anshul Kumar, CSE IITD                   slide 7
             Hazards in Pipelining

• Data dependencies => Data hazards
  – RAW (read after write)
  – WAR (write after read)
  – WAW (write after write)
• Resource conflicts => Structural hazards
  – use of same resource in different stages
• Procedural dependencies => Control hazards
  – conditional and unconditional branches, calls/returns

   Anshul Kumar, CSE IITD                           slide 8
                     Data Hazards
                                read/write
previous
  instr
                       read/write
current
 instr



                            delay = 3

   Anshul Kumar, CSE IITD                    slide 9
            Structural Hazards
              Caused by Resource Conflicts
• Use of a hardware resource in    A B A C
  more than one cycle                 A B A C
                                         A B A C

• Different sequences of
                                   A B C D
  resource usage by different
  instructions                        A C B D


• Non-pipelined multi-cycle        F D X X
  resources                           F D X X

Anshul Kumar, CSE IITD                          slide 10
                    Control Hazards
              cond eval                           target addr gen
 branch
  instr
next inline
   instr          delay = 2
  target
   instr                      delay = 5

   • the order of cond eval and target addr gen may be different
   • cond eval may be done in previous instruction

     Anshul Kumar, CSE IITD                                  slide 11
            Handling Data Hazards
    previous                  EX W
      instr
1                                Data Forwarding
    current                   R EX
     instr
    previous                    W
                                             Instruction
      instr
                                             Reordering

2

    current                          R
     instr
     Anshul Kumar, CSE IITD                        slide 12
  Analysis of Structural Hazards


  Non-linear
                               A           B       C
   Pipeline


                    1      2       3   4   5   6   7    8
Reservation Table A X                          X        X
      for X
                  B        X           X
                    C              X       X       X
  Anshul Kumar, CSE IITD                               slide 13
  Analysis of Structural Hazards


Multi-functional
                             A     B   C
   Pipeline


                    1 2 3 4 5 6         7    8
                    X
Reservation Table A Y       Y X              X
      for X
                  B   X Y X
      for Y
                     C      Y X   Y X Y X
   Anshul Kumar, CSE IITD                   slide 14
Collisions with Initiation Interval =2


     1     2      3        4     5     6     7     8     9     10 11
 A 1              2              3     1     4     1,2 5       2,3 6
 B         1               1,2         2,3         3,4         4,5
 C                1              1,2         1-3         2-4



  Anshul Kumar, CSE IITD                                         slide 15
Collisions with Initiation Interval =5


     1     2      3        4   5   6     7   8   9   10 11
 A 1                               1,2       1              2,3
 B         1               1             2       2
 C                1            1         1   2       2



  Anshul Kumar, CSE IITD                                 slide 16
 Latency Sequences and Cycles
1, 8, 1, 8, ….           (1, 8) avg = 4.5
3, 3, 3, 3, ….                  (3)       avg = 3
6, 6, 6, 6, ….                  (6)       avg = 6

Minimum Average Latency (MAL) ?




Anshul Kumar, CSE IITD                              slide 17
Collision Free Scheduling for X
                                       m ….   21
     Collision vector for X            1011010
          1 : collision
          0 : no collision
                              8+
                         1011010
              3                          8+
                    6    8+        1
       1011011                         1111111

          3         6

Anshul Kumar, CSE IITD                             slide 18
Collision Free Scheduling for Y
                                       m….2 1
     Collision vector for Y             1010
         1 : collision
         0 : no collision
                              5+
                          1010
                                       5+
                    3    5+        1
           1011                        1111

          3
Anshul Kumar, CSE IITD                          slide 19
Latency Cycles from State Diagram
 Latency Cycles
 (1, 8) (1, 8, 6, 8) (3) (6) (3, 8) (3, 6, 3)
 Simple Latency Cycles (no figure repeats)
 (1, 8) (3) (6) (3, 8) (6, 8)
 Greedy Latency Cycles
 (1, 8) (3) - from different starting states



  Anshul Kumar, CSE IITD                        slide 20
Minimum Average Latency (MAL)
 MAL > max no. of check marks in any row
 MAL < avg latency of any greedy cycle

 avg latency of any greedy cycle <
   no. of 1’s in initial collision vector + 1




 Anshul Kumar, CSE IITD                         slide 21
         Upper Bound on MAL

• Consider a greedy cycle (k1,k2,..,kn)
• Let p = no. of 1’s in initial collision vector
    k1 < p + 1
     k2 < 2 p - k1 + 2
     k3 < 3 p - k1 - k2 + 3
     ….
     kn < n p - k1 - k2 … - kn-1 + n
    k 1 + k2 … + k n < n p + n      MAL < p + 1
 Anshul Kumar, CSE IITD                         slide 22

				
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