2. Instruction-set Architecture Dr. John P. Abraham University of Texas - Panam Instruction-set architecture Introduction – 1. Datatypes are fundamental to all ISAs – 2. Register sets form the operational basis of an ISA – 3. Instruction set defines the operations the computer can perform and how it can reference the memory. Introduction contd. A Datatype is a set of values and operations defined on them. – Integer, what numbers are its members, what operations can it perform A register holds a value – The registers that the programmer can control are called operational registers Data representations Units of information Integers and Fractions Floating point numbers Data structures A byte is the basic unit of information A byte holds a character or a small integer. A word size is the size of its operational registers – A 16 bit computer has a word size of 2 bytes • A double word is 4 bytes Units of info contd. When a numeric representations uses a full word to represent a datum, it has single precision. When it uses 2 words, it has double precision One byte holds either ASCII OR EBCDIC Numeric data represented by: – 1. Binary coded decimal (BCD) – 2. Integer – 3. Floating point number Integers and Fractions Unsigned binary numbers (absolute numbers) – zero and positive integers Binary-coded Decimals – Use 4 bits to represent a decimal digit 0 - 9 (0000 to 1001) – 10010 to 1111 are not used for numbers, may be used for symbols such as $, % Signed-magnitude integers Left most bit stands for the sign bit (0 for positive and 1 for negative) the remaining bits holds the value of the number -2n-1 + 1 to +2n-1-1. Ones’ complement integers Positive integer has an absolute- binary representation, leading bit must be 0. – Representation of positive integers looks like signed-magnitude Negative numbers are represented as complements – Number -N is represented as 2n-1-N. One’s complement contd. Get the complement of the number – convert all 1s to 0s and 0s to 1 – positive 3 = 0011 – negative 3 = 1100 One’s complement allows for simpler addition, subtraction and multiplication circuitry Two’s-complement integers Positive numbers are represented same way as the sign-magnitued and one’s complement Negative number -N has the representation 2n-N. We first complement the bits and then add one to it. Positive 3 = 0011 -> 1100 ->1101 Excess-n Integers (bias-n) n + k where n is the bias if bias is 3 then number 12 is 1111 get less negative numbers Fractions A fraction is a quotient of two integers fraction is values between 0 and 1 order of bits from left to right 1/2, 1/4, 1/8, 1/16, 1/32 and so on Binary point (point symbol in a binary number) – Radix points - example octal point, hexadecimal points, etc. Floating -point Numbers floating points numbers are represented in four parts Sign, Mantissa (coefficient), radix, and exponent mantissa may be an integer (Burroghs, CDC), or fraction radixes are nearly always powers of 2 (2, 8 or 16) In scientific notations the radix is 10 Floating point Bits of a word encode the sign mantissa and exponent The hardware assumes the radix Normalized number 0.0001 e5 = 10 0.001 e4 = 10 repeatedly decreasing the exponent by 1 and shifting the mantissa left by one digit until the most significant digit is non-zero. The result is a normalized number. Normalized number contd. Since a normalized number starts with non zero number, in a binary number it always starts with a one. Since it always start with a one, this bit can be eliminated (eliding) and assumed by the hardware. After calculations the bit must be added back. Some floating point formats: Burroughs corporation B-5500 • Early example of floating point implementation • Both exponent and mantissa as signed- magnitude integers • Each word occupies 51 bits • Only 47 bits are used to store fp number • Exponent & its sign 7 bits • mangissa & its sign 40 bits • assumed radix is 8 Burroughs contd. Floating point and integer numbers use the same representation Integers have +0 exponent CDC Cyber 6000, 7000 and 170 integer mantissa biased-integer exponent each number is a 60 bit word. Leftmost bit is for sign, 48 bits forms one’s complement integer that is used as a mantissa. Remaning 11 bits are used as an excess-1024 integer exponent The radix is 2 IBM corporation system/370 Single precision is uses 32 bits Mantissa - normalized signed- magnitude hex fraction left most bit is sign, fractional part is the rightmost 24 bits Remaining 7 bits are used for the exponent (excess-64 integer) Radix is 16 Floating Point numbers in DEC (PDP-11 & VAX) single precision uses 32 bits 15th bit (start counting at 0) is the sign bit 0 thru 6 and 16 thru 31 are used for mantissa Redundant high order bit is elided. Exponent occupies 7 thru 14 (excess 128 integer) IEEE Floating-point standard Most microcomputers adapted this standard 32 bits are used 23 bits are used for mantissa – binary 1.00000 to bin1.1111111..1 – since 1 is always present it is elided – assumes the binary point is left of the first bit 8 bits for exponent (excess 127) 1 bit for the sign Data Structures Hardware to implement – character strings – stacks – arrays – parameter passage Character strings length string equal concat search for substring extracting substring Stacks LIFO push, pop, top, empty Arrays – Collections of data that have the same name – Array elements – Vectors and matrices Parameter passage see page 48 - self explanatory Precision of Basic datatypes the precision is fixed – Character sets – Integer – floating point Provision for variable-precision data Character - if more than 256 is needed escape sequence used. Integer - special provisions to use 8, 16, 32 or 64 bits – overflow bit may also be used Floating - single precision, double precision (32, 64 OR 128 bits) Block floating point Register Sets All von Neumann machines have a PC more or more registers for holding the instruction that is executing currently (IR - instruction register) Memory address register (MAR) - holds the address of memory which it is accessing MBR - memory buffer register holds data for store or receive data from a read. Register set contd. Index register - address displacement from base processor status bits or flags - – Positive-P, zero-Z, negative-N, carry-C, overflow-V, etc. Register Operations Computers may have several registers for – holding operands – holding results Instructions may specify – main-memory address – registers – both Register Operations cont. memory-to-register instructions – Instruction that access both main memory and registers memory-to-memory instructions – instructions that get operands from main memory and place their results in main memory (string operations) register-to-register instructions – get operands from registers and place their results in registers load-and-store instruction sets – read from memory and write to memory - no operations on data Register-register-instructions – Machines that provide more than one accumulator generally provide register-to-register instructions. – add instruction specifies two operand registers and one result register. – Register-to-register operations are much faster – RISC machines only have register-to- register instructions (except for load and store) Stack pointers Special registers called stack pointers to facilitate implementing stacks in memory. Stack pointers points to the top value in a stack the hardware automatically increments or decrements the stack pointer during push or pop. Factors to consider when designing for register sets: – Register-to-register operations are faster – each instruction must designate the register it will address • a computer needs large instructions to select among a large number of registers • N bits needed to select among 2N registers. – RISCs need to have large register sets. Factors contd. – Compilers tend to use a small number of registers because larger numbers are very difficult to use effectively. Hence providing a large register set is useless. – So there must be a balance. Register Architectures 0-address instructions – Instructions have only implicit operands and results – the op codes are very short – instructions execute very fast. 1-address instructions – instructions assume an accumulator and specify a single memory operand Register architectures contd. N-address instructions – instructions that specify N operand addresses (M+N)-address instructions – instructions that specy M operands and N branch address Evaluation-stack architectures implicitly takes its operands from a stack and places the results in the stack – an arithmetic instruction specifies an operation but not any operands. – ALU will reference a stack (stack in memory or hardware or both) – a PUSH instruction reads a value from memory and places it on the stack. – a POP instruction removes a value from the stack and stores in memory. Evaluation-stack architecture contd. – Once the stack holds a set of values, arithmetic instructions can operate on them. – Arithmetic instructions implicitly reference the top elements in the stack. – An ADD instruction would remove the top two stack elements and add them together and place the sum back on the stack. Evaluation-stack architecture contd. – a NEGATE instruction would simply change the sign of the top stack element. – Evaluation stack architectures excellent for arithmetic operations – difficult to to program text and string processing. – Burroghs B6700 uses evaluation-stack architecture. Accumulator machines – Use a single operational register called an accumulator. • Holds the result of an arithmetic, logical, or shift operation. • Also holds one of the operands for the operation. – The instruction does not explicitly reference the accumulator. • Accumulator is an implicit operand – each operate instruction holds the specification for one memory address. Accumulator machines contd. – Accumulator-machine instructions are 1- address instructions. • Shorter than 2 or three address instructions – An ADD instruction will have one address in memory for a single operand. • The data from the specified memory address is fetched • adds it to the value held in the accumulator • places the result in the accumulator. – Do not make explicit reference to the accumulator (it is implicit). Accumulator machines contd. – Accumulator machines require frequent memory accesses – slower than machines with multiple accumulators • multiple accumulator-machines make fewer memory accesses. General-purpose Register-set machines general purpose registers can be used as – accumulators – address registers – index registers – stack registers – program counters General purpose register set machines contd. Example: IBM system 370 and DEC VAX instruction specifies how the register will be used – may specify any number of register operands • register-to-register instructions • memory-to-memory instructions These machines have relatively fewer registers Special-purpose Register-set machines functions of registers are restricted. – One set may serve as index registers – another may only hold arithmetic operands, etc. – CDC6000/7000 family Many machines are neither special or general purpose, instead fall between the two. Type of instructions hardware components form the basis of computer’s capabilities instruction set determines its computational complexion. – Choose a set of datatypes – a set of operations on those datatypes – a set of techniques for address data in memory or gisters – specify logical flow of control Type of instructions contd. Operate instructions – initiate arithmetic, logical, and shift operations – move or translate data – manipulate stacks Character instructions – manipulate characters Character-string instructions – manipulate strings Vector instructions – vector operate, vector LOAD, and vector STORE Type of instructions contd. Memory Access instructions – Load, store Branch instructions – sub-routine-linkage instructions – conditional branch instructions I/O instructions – controls hardware operations – privilege level, interrupt hardware, memory protections, halt Operate instructions Operate instructions specify machine operations and therefore specify operands for those operations. An instruction may specify the operands implicitly or explicitly. – Operands specified by the opcode are implicit operands • example clear carry – most operands are specified explicitly. Operate instructions contd. Data operands are of two types – Immediate operands • data appear in the instruction stream (in the instructions themselves) – example AND(R1<--R1+#F7) - AND contents of R1 with F7h and place the result in R1 – F7h is the immediate operand and appears within the field of instruction – Addressed operand • the instruction specifies the address Arithmetic, logical and shift instructions Arithmetic, Logical and shift instructions – Add, subtract, multiply and divide – If the computer supports more than one numeric format or multiple precisions, it may provide different instructions for each type. – Processor status flags are set to indicate the outcome of the operation – product of n*n is 2n-1 bits long. So two registers are needed to store the result. – Integer division keeps the quotient in one register and remainder in another. Logical instructions – bitwise AND, OR, NOT, and XOR – Shift instructions: ROTATE LEFT, ROTATE RIGHT, LOGICAL SHIFT LEFT, LOGICAL SHIFT RIGHT, ARITHMETIC SHIFT RIGHT, ARITHMETIC SHIFT LEFT Character and String processing instructions – MOVE CHARACTER, MOVE STRING, COMPARE CHARACTERS, AND COMPARE STRINGS. Stack and Register Manipulation – push, pop, top, empty – register to register manipulations – LOAD IMMEDIATE – NO OP INSTRUCTION (does nothing) Memory-access instructions – load and store instructions • load instruction -specify size of the operand – load registers – store contents of registers to memory • load address - place effective address of the instruction itself into a base register • process synchronization instructions – for multitasking systems – synchronization primitives Processes active process – process that the processor is currently executing – can be a suspended process – can be a resumed process Inactive process – process that no processor is currently executing – cannot be resumed Shared variable and shared data set – Shared variable - data item in memory that several processes can access – Shared data set - data set that several processes can access – Order of operation is important Process A Process B A1 LOAD R1<--x B1 LOAD R1<--x A2 INCREMENT R1<--R1+1 B2 INCREMENT R1<--R1+1 A3 STORE X <--R1 B3 STORE X <--R1 The final value of X can be either X+1 or X+2 depending on the order. If Process a finishes before Process B then the answer is X+2 Try this: A1, B1, A2, B2, A3, B3 then the value is X+1 Order contd. – Critical sections - sections of code that update shared variables – Operating system should only allow one process to execute critical sections at a time • This method of synchronization is called MUTAL EXCLUSION. • In the previous slide, if the operating system enforces mutual exclusion, then the final value of X will always be X+2 Mutual exclusion implementations, some definitions. Atomic instruction - an operation that cannot be interrupted and other processes cannot access its operands or its result from the time it starts until it is finished. Locking - A process that blocks all other processes from accessing an entire data set that is being used. Mutual exclusion primitives TEST AND SET – operates on boolean variable in memory variables called semaphores are manipulated by setting TEST AND SET to TRUE, after manipulation set it to FALSE – most common primitive MATCH AND REPLACE - operates on three variables – Operates on three variables, say C, R, and S – Two of them, C and R, are within the processor – S is in the memory location Match & replace contd. – The match and replace instruction compares C to S and returns the result of the comparison to the processor. – If c and S are equal, it stores the value of R in S. – if C and S are unequal, no further action is taken – therefore, match and replace prevents all other processes from accessing the location holding S from the time it reads the stored value until it fishes udating the Fetch and increment – First, it loads the value of a variable into a register. – Then, it adds 1 to the value in memory – Fetch and add is a variation of Fetch and increment. It allows the programmer to add a variable to the value in the memory. Example: Test-and-set FLAG is a semaphore that is initially false No other process can update FLAG at the same time SPINLOCK: if TEST AND SET FLAG goto SPINLOCK – LOAD R1 <-- 1 – INCREMENT R1 <--R1+1 – STORE I <--r1 – CLEAR FLAG – <LOOP BODY> – goto SPINLOCK Control Instructions Conditional and Unconditional Brach Instructions Branch Test Subroutine-linkage Instructions Conditional and Unconditional Branch Instructions Conditional branching - Branch only if conditions are met – Branch instructions specify branch address as the operand – The branch target address is placed in PC Unconditional branching - Always branch regardless of conditions. Branch Test – an operand for conditional branch instructions. – The outcome of the test determines whether the branching should take place. • If it should CPU places the branch target address in the PC. Subroutine-linkage instructions Two subroutine linkage instructions are needed – one for branching • JSR (jump and save register) is a typical instruction – similar to branching except saves the contents of PC before branching – another for returning • Return – retrieves the address that was saved while branching – Entry point address and continuation point address Other instructions Miscellaneous – I/O instructions – Interrupts and State-Swapping Operations Privileged Instructions Vector Instructions I/O instructions – I/O instruction specifies the I/O device address and a code that tells the device what operation to perform. • I/O instructions: – input, output (reads or writes a byte) – test device - tests for a specified condition and sets a processor status bit. – control device - specifies a device specific operation to perform Interrupts and State-swapping Operations – interrupt is a hardware-initiated branch • it preserves enough information about the state of the program to restart it later – state-swapping • swapping the entire register set of one program with another. • Allows swapping controls between two programs rapidly Privileged instructions – Enable system software to protect itself. – Newer PCs do have privileged instructions – When a computer is booted, it starts out in privileged mode and then switches to the user mode. Vector instructions – Found on supercomputers and RISC machines – They perform identical operations on sequences of operands. – Load and store instructions should contain vector stride – A vector register is a set of registers that a vector instruction can reference individually or as a unit. Vector operate instructions – Monadic vector operations – Vector-scalar operations – Vector-vector operations – Vector-reduction operations Monadic and Vector-scalar operations – The simplest of the vector operations – performs the same computation on a sequence of consecutive variables in memory or registers, places the result in a different area Instructions: – copy - copies the elements of one vector to another, or copies a single scalar into all elements of a vector. – Negate - Vi changed to 0-Vi – Complement - Vi changed to NOT(Vi) – Reciprocal - Vi changed to 1/Vi – See figure 2.12 on page 74 Vector-vector operations – The sum (or any arithmetic or logical operation) of two vectors is formed by adding their corresponding elements and placing the results in a third vector – see figure 2.13 on page 74 Vector-reduction operation – Sum reduction - (column addition) : adds all of the elements in a vector – And/or reduction - perform AND (OR) on all of its elements together. • AND reduction gives true if all are true. OR gives true if any one is true – External reduction • finds the maximum or minimum of the elements of a vector. • combining a vector-vector operation with a vector reduction is called a dot product. Selection operation – If operations are required only on a selected vector elements, use a vector mask (test vector) • Suppose we need to select vector elements that are positive (nonnegative) • A vector mask is a logical vector (T/F) or a sequence of bits of 1 or 0 Selection operations – Comparison • A test-vector operation checks each elements of a vector to see if it satisfies a specified test condition, if so it sets the corresponding bet of a mask. – Merge • Takes selected elements of one vector and inserts them in another vector • Mask selects the elements to merge – Compression • Squeezes out unwanted elements specified by the mask – Expansion • inverse of vector compression Matrix operations – There are any number of ways to organize the elements of a matrix in the computers memory – Two most common ways are row-major and row-minor – Row major (Pascal) • Elements of the first row are stored in sequence followed by elements of second row and so on. – Row minor (Fortran) • Elements of first column are stored in sequence followed by second column Matrix operations – transpose • make a row major to column major or vice- versa – matrix product • see matrix operations on page 80 Addressing Techniques – When instructions specify operands, the operands may reside • in the instruction itself (immediate) • in main memory • in one or more operational registers – Ways of instructions can reference their operands. – Register addressing – boundary alignment – main memory addressing Register addressing (register operands) – Accumulator machines have just one implicit register operand which the instruction never specify – Register numbers (register designators) within the instructions select the registers for the CPU to use. – Register designators require 4 to 6 bits each (to address 16 (common) to 64 (maximum) registers). Boundary alignment – CPUs of most computers specify main- memory address as byte address rather than word address – Storage systems generally use word addresses and store and recall words. – For a 32 bit machine a word has four bytes. • Therefore a word address is the byte address divided by four • which is same as the byte address with low-order 2 bits truncated Boundary alignment contd. – During a load or store operation, the CPU gives the storage system the word address, which is the byte address with low-order 2 bits truncated. – When the storage system retrieves what is needed, the two low order bits are added by the cpu. – when using word address for storing and retrieving, it is called WORD BOUNDARY Boundary alignment contd. – Words that begin on word boundaries are called aligned words. – processor can access aligned words faster. – Page boundaries - when computers work with units called pages. Memory – Physical address is the address that the hardware uses to access a word. – Physical address is also called main- memory address. – Number of bits in the computer’s addressing hardware determines the maximum size of useable memory that computer can have. (n bits gives 2n addresses) – 20 bits gives 1 MB Memory contd. – To execute a program the OS allocates physical memory for the program – A loader loads the compiled program into memory with the aid of linker – During program execution the addressing hardware converts the instructions’ address specifications into effective addresses. (address resolution). – Effective address is used by CPU to reference addresses. – Effective address may be same as the physical address – On other systems the effective address should be further translated to physical address. • Perhaps by adding a constant • or by complex hardware maps as in virtual memory systems. Memory addressing Absolute addressing – an instruction containing effective address of an operand – simplest form of addressing. – Requires n bits to access 2n bytes of storage • 24 bits can reference 16mb of memory Register indirect addressing – instruction specifies an operational register, which holds the absolute address of the operand. Indexed addressing – Used with arrays. – The instruction can hold the address of the first element of A (address of the array). – The index register can hold the subscript of the array element. A(I) calculated automatically. (see page 89) Indirect addressing – address of memory location holding the value may be kept in another memory location. – The effective address specifies the cell in memory which holds an indirect address. – This indirect address is the operand address (see page 90) Indexed-indirect addressing – combines both indexed addressing and indirection • could be pre-indexed or post-indexed depending on when the index is added. Base-displacement addressing – A base register holds an effective address called the base address – A memory referencing instruction specifies both base register and a displacement. – The displacement is an immediate value in the instruction – The effective address is the sum of base and the displacement – may combine base-displacement with indexing.
Pages to are hidden for
"2. Instruction-set Architecture"Please download to view full document