Get documents about "Wafer Level Burn-in &
Document Sample
rev 2/04
Applied Wafer Test
Wafer Level Burn-In & Test (WLBT)
Presentation
“The Advanced Platform for
Wafer Level Burn-In”
Applied Wafer Test
Shared Vision…
“To become the partner of leading
semiconductor manufacturers in supplying
cost-effective test and burn-in solutions
optimized for DFT Methodologies”
May 21, 2012 "The advanced platform for WLBT" 2
This Presentation contains Confidential Information provided by Delta V Instruments and Covalar Research
Turnkey Solution for KGD
Covalar Research Motorola SMD
(Richardson, TX) (Chandler, AZ)
Design and develop Provide the processing
SM and test required to apply SM,
circuitry for cluster test and then remove
interface KGD the SM
Turnkey
Solution
Delta V Instruments Customer
(Richardson, TX)
Design, manufacture and Provides design knowledge
integrate wafer test and implements DFT
hardware structures into silicon
May 21, 2012 "The advanced platform for WLBT" 3
Why Wafer Level Burn-In & Test?
Process Control Feedback to the FAB
Reduced reaction time to implement corrective actions
Industry wants KGD and Multi-Chip Modules
WLBT provides a cost effective solution to producing
KGD when compared to Die Carrier solutions
WLBT provides cost effective reliability screening for
bare die
Manufacturing Cost Saving
Test and package costs saved by detecting defective
parts at the wafer level.
May 21, 2012 "The advanced platform for WLBT" 4
Our Solution . . .
A proven test platform: we can provide a turnkey
solution to the implementation of a WLBT process
Technology already used in
production by a leading
microprocessor manufacturer
Uses sacrificial metal layers
as an interconnect solution
Makes use of a clustering
scheme to limit test lines
May 21, 2012 "The advanced platform for WLBT" 5
Cluster Concept (Slide 1)
Package Level Burn-in
DRIVER BIB
Parallel set of vectors presented to all DUTs
Stimulus Vector
Generation
DUT DUT DUT DUT ... DUT
Monitoring
Individual DUT outputs monitored througout the burn-in cycle
May 21, 2012 "The advanced platform for WLBT" 6
Cluster Concept (Slide 2)
Wafer Level Burn-in
DRIVER WAFER
Vector, JTAG or BIST Stimulus
DUT DUT ... DUT DUT DUT ... DUT DUT DUT ... DUT
MUX MUX MUX
CLUSTER CLUSTER CLUSTER
Device Outputs
May 21, 2012 "The advanced platform for WLBT" 7
Cluster Concept (Slide 3)
DUT DUT
WAFER DUT DUT DUT DUT DUT DUT
DUT DUT DUT DUT DUT DUT DUT DUT
DUT DUT DUT DUT DUT DUT DUT DUT DUT DUT Vector, JTAG or Multiplexed
DUT DUT DUT DUT DUT DUT DUT DUT DUT DUT DUT DUT BIST Stimulus device
DUT DUT DUT DUT DUT DUT DUT DUT DUT DUT DUT DUT outputs
DUT DUT DUT DUT DUT DUT DUT DUT DUT DUT DUT DUT DUT DUT
DUT DUT DUT DUT DUT DUT DUT DUT DUT DUT DUT DUT DUT DUT
DUT DUT DUT DUT DUT DUT DUT DUT DUT DUT
DUT DUT DUT DUT
DUT DUT DUT DUT DUT DUT DUT DUT DUT DUT
DUT DUT DUT DUT DUT DUT DUT DUT
DUT DUT DUT DUT DUT DUT DUT DUT DUT
DUT DUT DUT DUT DUT DUT DUT
DUT DUT DUT DUT DUT DUT DUT DUT DUT
DUT DUT DUT DUT DUT DUT
DUT DUT DUT DUT DUT DUT DUT DUT
DUT DUT DUT DUT DUT
DUT DUT DUT DUT DUT DUT DUT
DUT DUT DUT
DUT DUT DUT DUT DUT DUT
DUT
DUT DUT CLUSTER
May 21, 2012 "The advanced platform for WLBT" 8
Cluster Test Configuration (Slide 1)
At the DUT Level
Vio
Vcore
0V
R(up/down) Monitor Lines
Fuse Links
DUT
R(isolation)
I/O Lines
May 21, 2012 "The advanced platform for WLBT" 9
Cluster Test Configuration (Slide 2)
At the Cluster Level
Vio
Vcore
0V
Monitor Lines
DUT DUT Up to 64
DUT
DUT/Cluster
I/O Lines
May 21, 2012 "The advanced platform for WLBT" 10
Cluster Test Configuration (Slide 3)
At the Wafer Level
Vio Rails
Vcore Rails
0V
Monitor Lines
CLUSTER CLUSTER Up to 512
CLUSTER
Cluster/Wafer
I/O Lines
May 21, 2012 "The advanced platform for WLBT" 11
Cluster Pin Allocation (example)
Addr Lines (A0-A19) - bank A
Addr Lines (A0-A19) - bank B
Scan Lines (1-40)
Ctrl Lines (1-10) - bank A
Ctrl Lines (1-10) - bank B
IO Lines (1-64)
PS1dut1
A(0-19) - bank A A(0-19) - bank B PS1dut2
S(1-10) S(1-10)
PS1dut3
CTRL(1-5) - bank A CTRL(1-5) - bank B
IO(1-16) IO(33-48)
PS1dut160
PS2dut1
DUTS 1-40 DUTS 81-120 PS2dut2
PS2dut3
A(0-19) - bank A A(0-19) - bank B
S(1-10) S(1-10) PS2dut160
CTRL(6-10) - bank A CTRL(6-10) - bank B
GND
IO(17-32) IO(49-64)
DUTS 41-80 DUTS 121-160
Wafer Stimulus Hardware
May 21, 2012 "The advanced platform for WLBT" 12
WLBT – Wafer Structure
Interconnect die clusters and provide interface to
sacrificial metal layer test hardware (signals and power). This layer would
be removed after production burn-in test
Used to protect die from circuit damage and allow
passivation layer
access to metal for probing and wire bonds
metalization layers Used to interconnect device structures on the die.
SM will make use of these layers for trace routing
Multiple layers used to define individual active
device structures (formed by repeating steps of
active device layers deposition, masking, etching and doping). Active
multiplexing circuitry and isolation resistors would
be added to the scribe lanes during this process
silicon base Used as a base to fabricate the wafer
May 21, 2012 "The advanced platform for WLBT" 13
WLBT – Sacrificial Metal Technique
a. Identify pads to be used
b. Route pads to scribe lanes
c. Place resistors in scribe lanes
d. Identify Cluster
e. Join individual die together
f. Add pads for contact to interface
g. After burn-in, remove sacrificial
metal layer, bump and dice the
die
May 21, 2012 "The advanced platform for WLBT" 14
WLBT – Sacrificial Metal Design Guidelines
Signal and Power
Pad Size (assuming standard pogo contact) 0.075” (1905µm)
Pad Pitch (sacrificial metal layer) 0.100” (2504µm)
Maximum Pads per Wafer (8”, 12”) 3000, 6500
Maximum Die per Cluster; Clusters per Wafer 64; 512
Pogo Contact (head diameter) 0.032” (813µm)
Maximum Icc per Pogo Contact 3A
Maximum I/O per wafer (4x stacked Drivers) 384
Number of Monitor lines per Cluster Multiplex as required
Resistor Values (Isolation, Pull Up/Down) 1K, 10K
May 21, 2012 "The advanced platform for WLBT" 15
Test Fixture Assembly
LN2 Supply
(opt.) Hot/Cold Chuck (opt.)
Driver Hot Chuck or Transfer Plate
Driver Wafer Mount
Pattern Generator Pogo Interface
Driver
Driver
Power Supplies (opt.)
PS Controller (opt.)
May 21, 2012 "The advanced platform for WLBT" 16
Test System Hardware
Supports 8” and 12” wafer formats
Provides up to 6,500 points of contact between the
wafer and the test circuitry
Wafers are loaded into fixtures which incorporate the
pogo contact interface
Uses 32mil pogo contacts for signal and power
Available with hot & cold thermal chucks
Supports up to 2kW power dissipation per wafer
Temperature range is -55°C to +180°C
Multiple Probes for Temperature Stability across the
wafer surface
May 21, 2012 "The advanced platform for WLBT" 17
Memory Stimulus Hardware
Memory Pattern Generator Module Memory Test Driver Module
(MPGM) - One per Wafer Test Fixture (MTDM) - Four per Wafer Test Fixture
May 21, 2012 "The advanced platform for WLBT" 18
Memory Pattern Generator (Slide 1)
4Gbits address range
36 Data Pattern Lines
16 Programmable DUT Clocks
40 Scan Lines
Algorithmic Micro-Code Sequencer
32 bit Address (16X + 16Y)
Test Cell and Index Counter
Incremental/decremental in row-fast or column-
fast mode
May 21, 2012 "The advanced platform for WLBT" 19
Memory Pattern Generator (Slide 2)
32K Vector RAM for arbitrary sequencies
ALU functions on counter and vector outputs
Software programmable address descrambling
3/2 2
Capable of order N, N , N patterns
Algorithmic pattern programming
Set of pre-defined background patterns
Software programmable data descrambling
8 Unique data patterns selectable on-the-fly
1nsec read strobe programming resolution
May 21, 2012 "The advanced platform for WLBT" 20
Memory Pattern Generator (Slide 3)
6 Internal Clocks
address multiplex
address invert
address output enable
data invert
data output enable
read strobe
32 Timing Sets
40nsec to 10microsec cycle length
10nsec programmable resolution
May 21, 2012 "The advanced platform for WLBT" 21
Memory Test Driver (Slide 1)
Independent signal levels for clock, address
and I/O lines
Programmable threshold (Vth) for I/O
comparators
Programmable super voltage (Vihh) for 8 clock
lines and 16 address lines
64 (32 + 32) address lines
72 I/O lines
32 (16 + 16) clock lines
May 21, 2012 "The advanced platform for WLBT" 22
Memory Test Driver (Slide 2)
32K failure log RAM
32 bits DUT address
36 bit expected data
72 bits failure data
15 bits sequencer data
8 bits scan bank
Maximum frequency
50Mhz (standard signals)
25Mhz (super voltage lines)
May 21, 2012 "The advanced platform for WLBT" 23
Memory Test Driver (Slide 3)
10 Ohm Output Impedance
200mA continuous drive current (2A peak)
<15nsec rise and fall time (2000pF, 0-5V 10-90%)
±5nsec maximum skew
Programmable Levels
Vih 0V to 10V
Vil -0.5V to 2V
Vihh 0V to 13V
Vth -2V to 10V
May 21, 2012 "The advanced platform for WLBT" 24
Memory Test Driver (Slide 4)
3 Independent programmable voltages
50mV resolution
±50mV accuracy
0V to 13V, 2A reference level
V1 Rail: 1.0V to 5.5V, 20A, 100W
V2 Rail: 1.0V to 5.5V, 20A, 100W
V3 Rail: 1.0V to 5.5V, 15A, 75W
May 21, 2012 "The advanced platform for WLBT" 25
Customer Plant Level Integration
Remote Operation data processing off-site
Local area network connects multiple test
systems with local operator control and
engineering support
Centralized data archiving
Direct feedback from data archive to process
flow
Driver platform common to both Package
Level Burn-in Test (PLBT) and WLBT
applications
May 21, 2012 "The advanced platform for WLBT" 26
Customer Considerations (Slide 1)
Test During Burn-In (TDBI) at Wafer Level
Provides immediate feedback to the FAB process
An increasing proportion of bare die have higher
complexity and speed which cannot be tested at
package level burn-in
Cost Savings
WLBT performed using DFT structures can
dramatically reduce the need for expensive ATE
WLBT catches early life failures (ELF) in marginal
and defective devices before wafers reach final
packaging and test
May 21, 2012 "The advanced platform for WLBT" 27
Customer Considerations (Slide 2)
The need for Known Good Die (KGD)
KGD is required for multi-chip modules and system-
on-chip (SOC) packages
WLBT will eliminate the need for special chip carriers
to heat and test bare die
What type of WLBT interface makes sense?
Simplicity of alignment between the production wafer
and the test electronics is critical to the test process
The interface design should take into account I/O fan
out, small die pitch, signal & power routing
May 21, 2012 "The advanced platform for WLBT" 28
Customer Considerations (Slide 3)
Electrical requirements
Die isolation is essential to perform effective testing
(must limit effect of bad die pulling high current)
Power dissipation per wafer can be high
Thermal management
Hot/Cold testing (-55ºC to +180ºC)
May 21, 2012 "The advanced platform for WLBT" 29
“The Advanced Platform for Wafer Level Burn-in”
Applied Wafer Test
would like to thank you for your time
and consideration.
May 21, 2012 "The advanced platform for WLBT" 30
