Sequential Logic by cz10mi1

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									Sequential Logic

          Lecture #7




                       1
강의순서
   Latch
   FlipFlop
   Shift Register
   Counter




모바일컴퓨팅특강             2
모바일컴퓨팅특강   3
SR Latch
   Most simple “storage element”.

                                NOR
                                In1       In2       Out
                                0         0         1
                                0         1         0
                                1         0         0
                                1         1         0

                                Function Table
                                 S    R         Q
Qnext = (R + Q’current)’         0    0   No change       Storing
Q’next = (S + Qcurrent)’         0    1   0 (reset)
                                 1    0    1 (set)




모바일컴퓨팅특강                                                            4
SR latches are sequential

   For inputs SR = 00, the next value   S   R          Q
    of Q depends on the current value    0   0    No change
    of Q.                                0   1    0 (reset)
                                         1   0     1 (set)
   So the same inputs can yield
    different outputs.
                                         Inputs    Current      Next
   This is different from the           S    R    Q    Q’      Q Q’
    combinational logics.                0   0      0       1   0   1
                                         0   0      1       0   1   0
                                         0   1      0       1   0   1
                                         0   1      1       0   0   1
                                         1   0      0       1   1   0
                                         1   0      1       0   1   0

모바일컴퓨팅특강                                                                5
Timing Diagram for S-R Latch

   S


   R


   Q


   Q’
           Set    Reset
모바일컴퓨팅특강                       6
SR latch simulation




모바일컴퓨팅특강              7
What about SR = 11?
   Both Qnext and Q’next will become 0.          Qnext = (R + Q’current)’
                                                  Q’next = (S + Qcurrent)’
   If we then make S = 0 and R = 0
    together,                                 0                              0
              Qnext = (0 + 0)’ = 1
              Q’next = (0 + 0)’ = 1
                                              0                              0
   But these new values go back into the
    NOR gates, and in the next step we get:
              Qnext = (0 + 1)’ = 0
              Q’next = (0 + 1)’ = 0
 The logic enters an infinite loop, where    0                              1
  Q and Q’ cycle between 0 and 1 forever.
  (Unstable)
 This is actually the worst case, so we
                                              0                              1
  have to
모바일컴퓨팅특강 avoid setting SR=11.                                                    8
An SR latch with a control input
(Gated SR latch)

                                          C   S   R   S’   R’      Q
                                          0   x   x   1    1    No change
                                          1   0   0   1    1    No change
                                          1   0   1   1    0    0 (reset)
                                          1   1   0   0    1     1 (set)
                                          1   1   1   0    0     Avoid!


   The dotted blue box is the S’R’ latch from the previous slide.
   The additional NAND gates are simply used to generate the
    correct inputs for the S’R’ latch.
   The control input acts just like an enable.


모바일컴퓨팅특강                                                                    9
D latch (Gated D latch)
   D latch is based on an S’R’ latch. The additional gates
    generate the S’ and R’ signals, based on inputs D (“data”)
    and C (“control”).
      When C = 0, S’ and R’ are both 1, so the state Q does not
       change.
      When C = 1, the latch output Q will equal the input D.
   Single input for both set and reset

                                                 C   D      Q
                                                 0   x   No change
                                                 1   0       0
                                                 1   1       1



 Also, this latch has no “bad” input combinations to avoid.
  Any of the four possible assignments to C and D are valid. 10
모바일컴퓨팅특강
Timing diagram for D Latch




           Q follows D while EN is HIGH.


모바일컴퓨팅특강                                   11
D latch with BDF




모바일컴퓨팅특강           12
D latch simulation with Primitive
   Insert the
    symbol latch




모바일컴퓨팅특강                            13
Simulation result with Primitive




모바일컴퓨팅특강                           14
D latch simulation with VHDL file




모바일컴퓨팅특강                            15
The D Flip-Flop : Edge triggering


                D1           Q1     D2           Q2
D                                                        Q
                       D                   D
                     Latch               Latch
                C            Q’     C            Q2’
C

• The D flip-flop is said to be “edge triggered” since the
  output Q only changes on the rising edge (positive
  edge) of the clock signal
모바일컴퓨팅특강                                                 16
Timing Diagram for a D-FF

 C


 D
                    shift


 Q1
                            shift

 Q



           Positive Edge Triggering
모바일컴퓨팅특강                              17
D-FF with Direct Inputs
   Most flip-flops provide direct, or asynchronous,
    inputs that immediately sets or clears the state.

   The below is a D flip-flop with active-low direct
    inputs.
                 S’   R’   C   D      Q
                 0    0    x   x    Avoid!
                 0    1    x   x    1 (set)    Direct inputs to set or
                 1    0    x   x   0 (reset)   reset the flip-flop
                 1    1    0   x   No change   S’R’ = 11 for “normal”
                 1    1    1   0   0 (reset)   operation of the D
                 1    1    1   1    1 (set)    flip-flop




모바일컴퓨팅특강                                                                 18
D-FF with BDF
   Insert the symbol dff



                            Edge-trigger symbol




모바일컴퓨팅특강                                          19
D-FF with VHDL file




모바일컴퓨팅특강              20
D-FF          with active-high Clock &
                             asynchronous Clear
  library ieee;
  use ieee.std_logic_1164.all;
  entity dff_1 is
  port( d, clk, nclr : in std_logic;
        q : out std_logic );
  end dff_1 ;
  architecture a of dff_1 is
  begin
       process(nclr,clk)
       begin
          if( nclr='0') then
            q <='0';
          elsif(clk'event and clk='1') then
            q <= d;
          end if;
       end process;
  end a;
모바일컴퓨팅특강                                          21
D-FF              with active- low Clock &
                                 asynchronous Clear
library ieee;
use ieee.std_logic_1164.all;
entity dff_fall_1 is
port( d, clk, nclr : in std_logic;
      q : out std_logic );
end dff_fall_1 ;
architecture a of dff_fall_1 is
begin
     process(nclr,clk)
     begin
        if( nclr='0') then
            q <='0';
        elsif(clk'event and clk=‘0') then
            q <= d;
        end if;
     end process;
end a;
 모바일컴퓨팅특강                                             22
D-FF           with active-high Clock &
                               asynchronous Preset
library ieee;
use ieee.std_logic_1164.all;
entity dff_ preset_1 is
port( d, clk, npre : in std_logic;
      q : out std_logic );
end dff_ preset_1 ;
architecture a of dff_ preset_1 is
begin
       process(npre,clk)
       begin
           if( npre='0') then
                q <=‘1';
           elsif(clk'event and clk=‘1') then
                q <= d;
           end if;
       end process;
end a;
모바일컴퓨팅특강                                             23
D-FF             with active-high Clock &
                        asynchronous Clear & Preset
library ieee; use ieee.std_logic_1164.all;
entity dff_ presetclr_1 is
port( d, clk, npre,nclr : in std_logic;
      q : out std_logic );
end dff_ presetclr_1 ;
architecture a of dff_ presetclr_1 is
begin
       process(npre, nclr, clk)
       begin
           if( npre='0') then
                q <=‘1';
           elsif( nclr='0') then
                q <=‘0';
           elsif(clk'event and clk=‘1') then
                q <= d;
           end if;
       end process;
end a;
모바일컴퓨팅특강                                              24
JK-FF & T-FF

   JK=11 are used to complement the flip-flop’s current state.
                                C   J   K       Qnext
                                0   x   x    No change
                                1   0   0    No change
                                1   0   1    0 (reset)
                                1   1   0     1 (set)
                                1   1   1     Q’current



   A T flip-flop can only maintain or complement its current
    state.
                                C   T       Qnext
                                0   x   No change
                                1   0   No change
                                1   1    Q’current
모바일컴퓨팅특강                                                        25
7474 Dual D-FF
   Insert the symbol others > quartus II > 7474




모바일컴퓨팅특강                                           26
7474 Dual D-FF “Datasheet” from
Philips
   Plastic dual in-line package




모바일컴퓨팅특강                           27
7474 Dual D-FF “Datasheet” from
Philips




모바일컴퓨팅특강                          28
Set-up and hold times
   For proper operation the D input to a D flip-flop should be
    stable for certain prescribed times before and after the
    rising clock edge. These are referred to as the set-up and
    hold times respectively




모바일컴퓨팅특강                                                          29
Set-up time (ts)
   The logic level must be present on the D input for a time
    equal to or greater than ts before the triggering edge of the
    clock pulse for reliable data entry.




모바일컴퓨팅특강                                                            30
Hold time (th)
   The logic level must remain on the D input for a time equal
    to or greater than th after the triggering edge of the clock
    pulse for reliable data entry.




모바일컴퓨팅특강                                                           31
D-FF timing constraints

  C



  D                       Hold time



  Q        Set-up time
                         Propagation delay

모바일컴퓨팅특강                                     32
Propagation Delay (1)
   As with any other circuit there will be a propagation delay
    between the rising edge of the clock and the time that the
    outputs of the flip-flop are stable.




모바일컴퓨팅특강                                                          33
Propagation delay (2)




모바일컴퓨팅특강                34
7474 Timing characteristics from datasheet




모바일컴퓨팅특강                                35
Clock Signal
   Periodic signal, generated by an oscillator which acts as
    the heartbeat of a synchronous digital system




           Clock Period

               Clock Frequency = 1 / Clock Period



모바일컴퓨팅특강                                                        36
Synchronous Systems
   In a synchronous system, all of the state elements
    are connected to the same clock signal.
   This means that they all change state at the same
    time.




모바일컴퓨팅특강                                             37
Timing Characteristics (1)

    Propagation delays
         through logic components (gates)
         through interconnects (routing delays)




             Gates             Gates                   Gates

               tp gates                   tp routing

           Total propagation delay through combinational logic



모바일컴퓨팅특강                                                         38
Timing Characteristics (2)
    Total propagation delay of logic (Sum of tp gate)
     depends on the number of logic levels and delays
     of logic components
          Number of logic levels is the number of logic
          components (gates) the signal propagates through
    Routing delays (tp routing) depend on:
         Length of interconnects
         Fanout



모바일컴퓨팅특강                                                     39
Timing Characteristics (3)
   Fanout – Number of inputs connected to one
    output
     •   Each inputs has its capacitance
     •   Fast switching of outputs with high fanout requires
         higher currents  This makes a larger delay.


                                Gates
                                             Gates
                  Gates         Gates

모바일컴퓨팅특강                                                       40
Timing Characteristics (4)

   In Current Technologies Routing Delays Make
    50-70% of the Total Propagation Delays




모바일컴퓨팅특강                                          41
Critical Path & Cycle Time

Clk



        .     .                                 .    .
        .     .                                 .    .
        .     .                                 .    .




     Critical path: the slowest path between any two storage
      devices
     Cycle time is a function of the critical path
     must be greater than:
       Clock-to-Q + Longest Path through Combinational Logic +
         Setup
Critical Path

   Min. Clock Period = Length of The Critical Path
   Max. Clock Frequency = 1 / Min. Clock Period




모바일컴퓨팅특강                                              43
Clock Jitter
     Rising Edge of The Clock Does Not Occur
      Precisely Periodically
         May cause faults in the circuit

      clk




모바일컴퓨팅특강                                        44
Clock Skew
   Rising Edge of the Clock Does Not Arrive at Clock
    Inputs of All Flip-flops at The Same Time


        in                                          out
              D   Q                         D   Q


        clk
                          delay


        in                                          out
              D   Q                        D    Q


                                          clk
                          delay
모바일컴퓨팅특강                                                  45
Dealing With Clock Problems
   Use Only Dedicated Clock Nets for Clock Signals

   Do Not Put Any Logic in Clock Nets




모바일컴퓨팅특강                                              46
Register
   Flip-Flip을 응용한 데이터 저장장치
       가장 기본적인 순차논리회로
   Multi-bit Register
   Shift Register
   Counter Register




모바일컴퓨팅특강                      47
8-bit register with asynchronous reset
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY reg8 IS
    PORT ( D                    : IN    STD_LOGIC_VECTOR(7 DOWNTO 0) ;
               Resetn, Clock    : IN    STD_LOGIC ;
               Q                : OUT   STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;
END reg8 ;

ARCHITECTURE Behavior OF reg8 IS
BEGIN
    PROCESS ( Resetn, Clock )
                                                      8         Resetn      8
    BEGIN
         IF Resetn = '0' THEN                               D           Q
              Q <= "00000000" ;
         ELSIF Clock'EVENT AND Clock = '1' THEN
              Q <= D ;                                          Clock
         END IF ;
    END PROCESS ;                                               reg8
END Behavior ;`
모바일컴퓨팅특강                                                                        48
N-bit register with asynchronous reset
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY regn IS
     GENERIC ( N : INTEGER := 16 ) ;
     PORT (    D               : IN        STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
               Resetn, Clock   : IN        STD_LOGIC ;
               Q               : OUT       STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END regn ;

ARCHITECTURE Behavior OF regn IS
BEGIN
     PROCESS ( Resetn, Clock )                                N           Resetn      N
     BEGIN
          IF Resetn = '0' THEN
                                                                      D           Q
                Q <= (OTHERS => '0') ;
          ELSIF Clock'EVENT AND Clock = '1' THEN
                Q <= D ;                                                  Clock
          END IF ;
     END PROCESS ;
                                                                          regn
END Behavior ;
모바일컴퓨팅특강                                                                                  49
N-bit register with Enable
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY regn IS
     GENERIC ( N : INTEGER := 8 ) ;
     PORT (    D                 : IN       STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
               Enable, Clock     : IN       STD_LOGIC ;
               Q                 : OUT      STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END regn ;

ARCHITECTURE Behavior OF regn IS
BEGIN                                                        N          Enable      N
     PROCESS (Clock)
     BEGIN                                                          D           Q
          IF (Clock'EVENT AND Clock = '1' ) THEN
                IF Enable = '1' THEN
                      Q <= D ;                                          Clock
                END IF ;
          END IF;                                                       regn
     END PROCESS ;
END Behavior ;
모바일컴퓨팅특강                                                                                50
Shift register

                         Q(3)           Q(2)           Q(1)           Q(0)


           Sin
                 D   Q          D   Q          D   Q          D   Q


    Clock

    Enable




모바일컴퓨팅특강                                                                     51
  Shift Register With Parallel Load
Load

D(3)
                   D(2)           D(1)           D(0)
Sin


               D   Q          D   Q          D   Q          D   Q



       Clock




Enable

  모바일컴퓨팅특강                                                          52
                       Q(3)           Q(2)           Q(1)           Q(0)
4-bit shift register
              with parallel load (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY shift4 IS
    PORT ( D             :   IN        STD_LOGIC_VECTOR(3 DOWNTO 0) ;
               Enable    :   IN        STD_LOGIC ;
               Load      :   IN        STD_LOGIC ;
               Sin       :   IN        STD_LOGIC ;
               Clock     :   IN        STD_LOGIC ;
               Q         :   BUFFER    STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END shift4 ;

                                4      Enable    4
                                      D     Q
                                      Load
                                      Sin
                                                     shift4
모바일컴퓨팅특강                                                                  53
                                       Clock
4-bit shift register
              with parallel load (2)
ARCHITECTURE Behavior_1 OF shift4 IS
BEGIN
        PROCESS (Clock)
        BEGIN
                 IF Clock'EVENT AND Clock = '1' THEN
                           IF Load = '1' THEN
                                      Q <= D ;
                           ELSIF Enable = ‘1’ THEN
                                      Q(0) <= Q(1) ;
                                      Q(1) <= Q(2);    4             4
                                                            Enable
                                      Q(2) <= Q(3) ;
                                      Q(3) <= Sin;         D     Q
                           END IF ;                        Load
                 END IF ;                                  Sin
        END PROCESS ;                                                    shift4
END Behavior_1 ;                                            Clock


모바일컴퓨팅특강                                                                    54
N-bit shift register
              with parallel load (1)
 LIBRARY ieee ;
 USE ieee.std_logic_1164.all ;

 ENTITY shiftn IS
           GENERIC ( N : INTEGER := 8 ) ;
           PORT (   D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
                    Enable    : IN     STD_LOGIC ;
                    Load      : IN     STD_LOGIC ;
                    Sin       : IN     STD_LOGIC ;
                    Clock     : IN     STD_LOGIC ;
                    Q         : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
 END shiftn ;


                                 N    Enable   N
                                     D     Q
                                     Load
                                     Sin
                                                   shiftn
모바일컴퓨팅특강                                                                    55
                                      Clock
N-bit shift register
              with parallel load (2)
ARCHITECTURE Behavior OF shiftn IS
BEGIN
        PROCESS (Clock)
        BEGIN
                 IF (Clock'EVENT AND Clock = '1' ) THEN
                            IF Load = '1' THEN
                                       Q <= D ;
                            ELSIF Enable = ‘1’ THEN
                                       Genbits: FOR i IN 0 TO N-2 LOOP
                                                 Q(i) <= Q(i+1) ;
                                       END LOOP ;
                                       Q(N-1) <= Sin ;
                            END IF;
                 END IF ;                                   N      Enable   N
        END PROCESS ;                                             D     Q
END Behavior ;                                                    Load
                                                                Sin
                                                                                shiftn
모바일컴퓨팅특강                                                         Clock             56
2-bit up-counter
        with synchronous reset
 LIBRARY ieee ;
 USE ieee.std_logic_1164.all ;
 USE ieee.std_logic_unsigned.all ;
 ENTITY upcount IS
      PORT ( Clear, Clock : IN            STD_LOGIC ;
                Q              : BUFFER   STD_LOGIC_VECTOR(1 DOWNTO 0) ) ;
 END upcount ;

 ARCHITECTURE Behavior OF upcount IS
 BEGIN
     upcount: PROCESS ( Clock )                                          2
     BEGIN                                                   Clear
                                                                     Q
          IF (Clock'EVENT AND Clock = '1') THEN
                IF Clear = '1' THEN                         upcount
                     Q <= "00" ;
                ELSE
                                                             Clock
                     Q <= Q + “01” ;
                END IF ;
          END IF;
     END PROCESS;
모바일컴퓨팅특강                                                                     57
 END Behavior ;
4-bit up-counter
        with asynchronous reset (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;

ENTITY upcount IS
    PORT ( Clock, Resetn, Enable       : IN    STD_LOGIC ;
            Q             : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ;
END upcount ;


                                    Enable   4
                                         Q

                                    Clock
                                             upcount
                                    Resetn

모바일컴퓨팅특강                                                           58
4-bit up-counter
        with asynchronous reset (2)
ARCHITECTURE Behavior OF upcount IS
        SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ;
BEGIN
        PROCESS ( Clock, Resetn )
        BEGIN
                IF Resetn = '0' THEN
                         Count <= "0000" ;
                ELSIF (Clock'EVENT AND Clock = '1') THEN
                         IF Enable = '1' THEN
                                  Count <= Count + 1 ;
                         END IF ;                        Enable    4
                END IF ;                                       Q
        END PROCESS ;
        Q <= Count ;                                      Clock
END Behavior ;                                                     upcount
                                                         Resetn

모바일컴퓨팅특강                                                               59
 4 bits Universal Counter: 74161
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt161_4bits is                                 74161은 실제로 가장 널리
port( d3,d2,d1,d0 : in std_logic;                       사용되는 4비트 카운터임
       nld,ent,enp : in std_logic;
       clk,nclr         : in std_logic;
       q3,q2,q1,q0 : out std_logic;
       rco               : out std_logic);
end cnt161_4bits;
architecture a of cnt161_4bits is
     signal q : std_logic_vector( 3 downto 0);
begin
     process(nclr,clk)
     variable d : std_logic_vector(3 downto 0);
     begin
          d := d3&d2&d1&d0;
          if( nclr='0') then q <="0000";
          elsif(clk'event and clk='1') then
               if(nld='0') then q <= d;
               elsif(ent='1' and enp='1') then
                    q <= q+'1';
               end if;
          end if;
     end process;
     q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0);
     rco <= ent and q(3) and q(2) and q(1) and q(0);
end a;
 모바일컴퓨팅특강                                                             60
Modulo 16 Up Counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mod16cnt is
port( clk,nclr : in std_logic;
    q3,q2,q1,q0 : out std_logic);
end mod16cnt;
architecture a of mod16cnt is
     signal q : std_logic_vector( 3 downto 0);
begin
     process(nclr,clk)
     begin
          if( nclr='0') then q <="0000";
          elsif(clk'event and clk='1') then
               q <= q+'1';
          end if;
     end process;
     q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0);
end a;
 모바일컴퓨팅특강                                        61
  Modulo 16 Down Counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mod16dncnt is
port( clk,nclr       : in std_logic;
    q3,q2,q1,q0 : out std_logic);
end mod16dncnt;
architecture a of mod16dncnt is
     signal q : std_logic_vector( 3 downto 0);
begin
     process(nclr,clk)
     begin
          if( nclr='0') then q <="0000";
          elsif(clk'event and clk='1') then
               q <= q-'1';
          end if;
     end process;
     q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0);
end a;
  모바일컴퓨팅특강                                       62
  Modulo 16 Up Down counter
library ieee; use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;                1이
                                                면증
entity UpDncnt4 is                               가

port( clk,nclr       : in std_logic;
      UpDn       : in std_logic;
    q3,q2,q1,q0 : out std_logic);
end UpDncnt4;
architecture a of UpDncnt4 is
    signal q : std_logic_vector( 3 downto 0);
begin
    process(nclr,clk)                                0 이면
    begin                                             감소

        if( nclr='0') then q <="0000";
        elsif(clk'event and clk='1') then
             if( UpDn='1') then q <= q+'1';
             else q <= q-'1';
             end if;
        end if;
    end process;
    q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0);
   모바일컴퓨팅특강                                                 63
end a;
 Modulo 15 Up Counter
library ieee; use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mod15cnt is
port( clk,nclr : in std_logic;
     q3,q2,q1,q0 : out std_logic);
end mod15cnt;
architecture a of mod15cnt is
   signal q : std_logic_vector( 3 downto 0);
begin
   process(nclr,clk)                           14에서
   begin                                       0 으로
                                                증가
      if( nclr='0') then
           q <="0000";
      elsif(clk'event and clk='1') then
           if( q="1110") then
                 q<="0000";
           else q <= q+'1';
           end if;
      end if;
   end process;
   q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0);
end a;
 모바일컴퓨팅특강                                        64

								
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