# State University of New York at Stony Brook

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```					      Computer Science Department
Hofstra University

Introduction to computer architecture (lab.)
CSC 110-A
Spring 2004

Lab # 7

Instructor: Dr. Simona Doboli
1. Objectives
The goal of this lab is to test the functionality of a D flip flop and to build a bidirectional
universal shift register.

2. Introduction

a) D flip-flops

A D FF is a memory circuit that propagates the value from the input to the output only when
a second input - the clock - transitions from high to low - negative edge triggered flip-flop - or
low to high - positive edge triggered flip-flop. A D FF is build with combinational circuits,
and has two main parts: a master and a slave circuits.

The block diagram of a D FF is presented in Figure 1.

Figure 1. Block diagram of a D flip-flop

The D input is the data input, the CLK input is the clock input. There are two outputs: Q and
its complement Q'. The Preset input when active (0 V) sets the Q output to 1, while an active
Clear input (0 V) sets the Q output to 0. The Preset and Clear inputs override the CLK and D
inputs, meaning that when one of them is active, the Q output will be set according to them,
not to the value of the D or CLK signal. If both Preset and Clear are activate (e.g. both are
connected to 0 V), then the Preset input has precedence and both Q and Q' outputs are set to
1. The value of the D input is seen at the output only when the CLK input transitions from
low to high values and the Preset and Clear inputs are inactive. Between transitions of the
clock, the Q output remains unchanged, and any changes of the D input are not seen at the
output.

An integrated circuit containing 2 D FF is 74LS74. Its block diagram is in Logic Works or
Engineering Manual.

b) 4-bit bidirectional universal shift register using D FF

A shift register with n bits shifts its data by one bit at a time at each clock transition. A
unidirectional shift register shifts its data in one direction only (left or right). A register that
can shift in both directions is a bi-directional shift register.
A shift register has a serial input that specifies the bit to be shifted into one end of the register
at each clock tick. A register with parallel input, can have all its bits set to an external set of
values on one clock transition. Such a register is called parallel-in, parallel-out shift register.

The block diagram of a parallel-in, parallel-out shift register is shown in Figure 2.

Figure 2. Block Diagram of a parallel-in, parallel-out shift register.

When the Load/Shift input is 0, the output is shifted by one position at each positive clock
edge (shift operation). The value that is introduced at the right end of the register is
determined by the Serial In input. When the Load/Shift input is 1, the external values
(E0,..,E3) are loaded in the register at the next positive clock edge (parallel load operation).

You have to build an universal bi-directional shift-register (it can shift either left or right)
with the following functionality controlled by two selection inputs s1s0:

    When s1s0= 00, the present value of the register (e.g. the values of the Q outputs) is
applied to the D inputs and the outputs remain unchanged at the next clock edge (e.g.
the register is recharged with the output values: The D inputs are equal to Q outputs).
    When s1s0= 01, the register does a shift right operation at the next clock edge.
    When s1s0= 10, the register does a shift left operation at the next clock edge.
    When s1s0= 11, the register is loaded (parallel load) with the external input values
(E0, ..., E3) at the clock edge (the parallel load operation).
2. Preliminary Lab

You must complete following design and simulation steps before building the circuits:

1. Step 1: Build the circuit in Figure 1 in Logic Works using 74LS74 IC. Connect binary
switches at the inputs of one of the D FF, and binary probes at the outputs. Add all the
input and outputs to the timing diagram.

2. Step 2: Simulate the circuit. Fill out a table that shows how the outputs are modified in
relation to what happens at the input. Check how the state of the D FF (e.g. the Q and Q'
outputs) changes in response to clock transitions. Check how the state of the D FF
changes in responses to changes in the Preset and Clear inputs.

3. Step 3: Build the shift register circuit shown in Figure 2 in Logic Works. Use 74LS74 for
the D FF. Instead of the 2 AND 1 OR gates you can also use a 2X1 MUX. In any case,
use a subcircuit for the MUX functionality. Add all inputs and outputs to the timing
diagram.

4. Step 4: Simulate the circuit. Fill out a table showing the results for the tests you tried.
You have to test both the shift operation and the external load operation.

5. Step 5: Design a bi-directional universal shift register. Its functionality is described in the
introduction.

6. Step 6: What would be a small number of test cases (inputs) that you would use to test
the functionality of the universal circuit? What are those cases?

7. Step 7: How do you plan to trouble shoot your circuit?

Your solutions for Steps 1-7 will be presented in the prelab. You have to include circuit
diagrams, result tables, and timing diagrams showing different values of the input and output
signals.

3. Lab

During the lab hours, you will do the following tasks:

1. D FF:

Step 1: Implement the circuit shown in Figure 1 on Protoboard (use 74LS74 IC).
Connect the inputs to switches (use resistors for the switches - a description of how
switches work is given in Lab 1 of the manual). Connect all the inputs and outputs to
LEDs.

Step 2: Verify the D FF operation for the test cases you used in the Prelab at Step 2.

2. 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER:

Step 3: Build the 4 BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER in
Logic Works. Use the design you proposed at Step 5 of the Prelab.
Step 4: Simulate its operation for the test cases you proposed at Step 6 of the Prelab.

Notes: If outputs are incorrect then use the trouble shooting strategies you identified at Step 7 of
the Prelab.

Pre Lab

Step                     Max Grade (# of points)                    Scored
Step 1                             15
Step 2                             15
Step 3                             15
Step 4                             20
Step 5                             20
Step 6                             10
Step 7                              5

Lab

Step                     Max Grade (# of points)                    Scored
Step 1                             20
Step 2                             30
Step 3                             20
Step 4                             30

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