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Low-Power CMOS Logic Circuit
Topic Review
Part I: Overview (Shaw)
Part II: (Vincent)
•Low-Power Design Through Voltage Scaling
•Estimation and Optimization of Switching Activity
Part III: (Shaw)
•Reduction of Switched Capacitance
•Adiabatic logic circuit
1
Low-Power CMOS Logic Circuit
Topic Review
Introduction
2
Low-Power CMOS Logic Circuit
Topic Review
Motivations:
Portability
Notebook computer
Portable communication devices
Personal digital assistants (PDAs)
Green Computer
"The computer must be designed to use only non-toxic
materials, to be energy efficient, and to have minimal impact
on the environment in every stage of its life cycle."
Reliability
3
Low-Power CMOS Logic Circuit
Topic Review
Methods?
Device level: Device characteristics (e.g., threshold voltage),
device geometries, and interconnect properties.
Circuit level: proper choice of circuit design styles, reduction
of the voltage swing, and clocking strategies.
Architecture level: smart power management of various
system blocks, utilization of pipelining and parallelism, and
design of bus structure.
Algorithm level: minimize the number of switching events.
4
Low-Power CMOS Logic Circuit
Topic Review
Overview
Types of Power Consumption
5
Low-Power CMOS Logic Circuit
Topic Review
Three main components (CMOS circuit):
1. Dynamic (switching) power consumption
2. Short-circuit power consumption
3. Leakage power consumption
6
Low-Power CMOS Logic Circuit
Topic Review
1. Switching Power Dissipation:
Charge-up: one-half of
the energy drawn from the
power supply is dissipated as
heat in conducting pMOS
transistors.
Charge-down: no
energy is drawn from the
power supply during the
charge-down phase, yet the
energy stored in the output
capacitance during the charge-
up is dissipated as heat in the
conducting nMOS transistors.
7
Low-Power CMOS Logic Circuit
Topic Review
n n
Cload Cdrain Cint erconnect Cinput
i 1 i 1
1 dVout
T /2
dVout T
Pavg Vout (Cload )dt (VDD Vout )(Cload )dt
T0 dt T /2 dt
VDD to 0 0 to VDD
(Periodic input with ideally zero rise- and fall-times)
Assumption: output undergoes
transition
Pavg Cload VDD fCLK
2
Reality? Node transition rate can be slower
than the clock rate!
Pavg T Cload V 2 DD fCLK
T Node transition factor 8
Low-Power CMOS Logic Circuit
Topic Review
Ci
# of nodes
Pavg Ti Ci Vi VDD f CLK
i 1
Represents the parasitic capacitance associated with
Ci each node in the circuit (including the output node)
Represent the corresponding node transition factor
Ti associated with that node 9
Low-Power CMOS Logic Circuit
Topic Review
2. Short-Circuit Power Dissipation:
10
Low-Power CMOS Logic Circuit
Topic Review
Conditions: smaller output load capacitance
and larger input transition times
11
Low-Power CMOS Logic Circuit
Topic Review
Conditions: symmetric CMOS inverter with k n k p k
VT ,n VT , p VT
Very small capacitive load
rise fall
1 k f CLK
I avg ( short circuit) (VDD 2VT )3
12 VDD
1
Pavg (short circuit) k f CLK (VDD 2VT )3
12
Short-circuit power dissipation Input signal rise and fall times
12
Low-Power CMOS Logic Circuit
Topic Review
Conditions: larger output load capacitance
and smaller input transition times
13
Low-Power CMOS Logic Circuit
Topic Review
3. Leakage Power Dissipation:
Reverse diode leakage current & subthreshold current
(Reverse diode leakage current)
14
Low-Power CMOS Logic Circuit
Topic Review
qVbias
I reverse A J s (e kT
1)
Vbias Reverse bias voltage across the junction
Js Reverse saturation current density. The
typical reverse saturation current density
is 1 5 pA / m 2
A Junction area
15
Low-Power CMOS Logic Circuit
Topic Review
(subthreshold current)
q q
qDnWxc n0 r
( AVGS BVDS )
I D ( subthreshold ) e e kT
kT
LB
16
Low-Power CMOS Logic Circuit
Topic Review
4. Examples of Actual Power Dissipation:
Chip Intel DEC Alpha 21064 Cell based ASIC
80386
Minimum feature size 1.5 m 0.75 m 0.5 m
Number of gates 36,808 263,666 10,000
Clock frequency f CLK 16MHz 200MHz 110MHz
Supply voltage 5V 3.3V 3V
Total power dissipation 1.41W 32W 0.8W
Logic gates 32% 14% 9%
Clock distribution 9% 32% 30%
Interconnect 28% 14% 15%
I/O drivers 26% 37% 43%
17
Low-Power CMOS Logic Circuit
Topic Review
Summary
In addition to the three major sources of power
consumption in CMOS digital integrated circuits
discussed in this section, some chips may also contain
circuits which consume static power. One example is
the pseudo-nMOS logic circuits which utilize a pMOS
transistor as the pull-up device.
Ptotal T Cload V 2 DD fCLK VDD (I short circuit Ileakage I static )
18
Low-Power CMOS Logic Circuit
Topic Review
Method #1: Reduction of Switched Capacitance
System-Level
Measures:
1. Large number of
drivers and
receivers sharing
the same
transmission
medium
2. The parasitic
capacitance of the
long bus line.
19
Low-Power CMOS Logic Circuit
Topic Review
Circuit-Level The capacitance is a function of the
Measures: number of transistors that are required to
implement a given function
Pass-gate logic CMOS circuit
XOR logic 20
Low-Power CMOS Logic Circuit
Topic Review
Mask-Level
Measures:
The parasitic gate and diffusion capacitances
of MOS transistors in the circuit typically
constitute a significant amount of the total
capacitance in a combinational logic circuit.
Hence, a simple mask-level measure to reduce
power dissipation is keeping the transistors
(especially the drain and source regions) at
minimum dimensions whenever possible and
feasible.
21
Low-Power CMOS Logic Circuit
Topic Review
minimum dimensions??
Trade-off:
Dynamic performance of the circuit Power dissipation
22
Low-Power CMOS Logic Circuit
Topic Review
Method #2: Adiabatic Switching
Adiabatic switching is also called energy-recovery
“Adiabatic” describe thermodynamic process that
exchanges no heat with the environment
Keep potential drop switching device small
Allow the recycling of energy to reduce the total
energy drawn from the power supply
23
Low-Power CMOS Logic Circuit
Topic Review
CMOS Switching
0 to VDD Transition of the output: Q Cload VDD
Esup ply CloadV 2 DD
How much is the stored energy? E store Cload V 2 DD / 2
No charge is drawn from the power
VDD to 0 Transition of the output:
supply and the the energy stored in the
load capacitance is dissipated in the
nMOS network
24
Low-Power CMOS Logic Circuit
Topic Review
Adiabatic Switching:
25
Low-Power CMOS Logic Circuit
Topic Review
1
VC (t ) I source t
C Less dissipation only if:
V (t )
I source C C
t
–Current is constant and T 2RC
T Least power dissipation <- slowest transition
Ediss R I 2 sourcedt R I 2 source T Energy dissipation is not only depend on the
0 capacitance and swing voltage, but also
RC proportional to the output resistance.
Ediss CV 2 C (T )
T
26
Low-Power CMOS Logic Circuit
Topic Review
An example of Adiabatic Switching:
Adiabatic amplifier circuit which transfers the complementary
input signals to its complementary outputs through CMOS
transmission gates
27
Low-Power CMOS Logic Circuit
Topic Review
Adiabatic Logic Gates:
The general circuit topology of a The topology of an adiabatic logic
conventional CMOS logic gate gate implementing the same
function 28
Low-Power CMOS Logic Circuit
Topic Review
Circuit diagram of an adiabatic CMOS
29
Low-Power CMOS Logic Circuit
Topic Review
Stepwise Charging Circuits:
A CMOS inverter circuit with a stepwise-increasing supply voltage
30
Low-Power CMOS Logic Circuit
Topic Review
Equivalent circuit, and the input and output voltage
waveforms of the CMOS inverter circuit
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Low-Power CMOS Logic Circuit
Topic Review
Analysis:
( i 1)
dVout VA Vout
ic C
dt R
Solving this differential equation with the
initial condition Vout (ti ) VA
(i )
( i 1) Vdd t / RC
Vout (t ) VA e
n
2
1 Vdd
ic Rdt 2 C
2
Estep
0
n 2
2
1 V
Etotal n Estep C dd
n 2
32
Low-Power CMOS Logic Circuit
Topic Review
Stepwise driver circuit for capacitive loads. The load capacitance is
successively connected to constant voltage sources Vi through an
array of switch devices
33
Low-Power CMOS Logic Circuit
Topic Review
Tradeoff!!
Reduction of energy Expense of switching
dissipation time
34
Low-Power CMOS Logic Circuit
Topic Review
Adiabatic families:
Partially Adiabatic Logic
–2N2P / 2N-2N2P
–CAL (Clocked CMOS Adiabatic Logic)
–TSEL (True Single Phase Adiabatic)
–SCAL (Source-coupled Adiabatic Logic)
Fully Adiabatic Logic
–PAL (Pass-transistor Adiabatic Logic)
–Split-level Charge Recovery Logic (SCRL)
35
Low-Power CMOS Logic Circuit
Topic Review
Periodic ramp-like
2N2P Inverter vs CMOS Inverter clocked power
supply
Vdd PC
o o
out /out
in /in
out
in o
Q=CV I=Q/T; T
Pavg Cload VDD fCLK
2 Edcharge I 2 RT IRQ
CMOS Inverter 2N2P Inverter
36
Low-Power CMOS Logic Circuit
Topic Review
37
Low-Power CMOS Logic Circuit
Topic Review
38
Low-Power CMOS Logic Circuit
Topic Review
39
Low-Power CMOS Logic Circuit
Topic Review
2N-2N2P Inverter
The primary advantage
of 2N-2N2P over 2N2P is
that the addition of the
cross-coupled Nfets results
in non-floating data valid
over 100% of the HOLD
phase. 40
Low-Power CMOS Logic Circuit
Topic Review
Analysis:
Reset Phase:
•The high output will ride down
only to Vt,p, rather than GND.
Wait Phase:
•Floating at 0 and Vt,p
Evaluation Phase:
•If State has not changed
•If changed(nonadiabatic power
consumption is CVt , p )
2
41
Low-Power CMOS Logic Circuit
Topic Review
Characteristics of 2N2P / 2N-2N2P
Cascades require four-phase clocks
Non-adiabatic occurs at brief interval in the beginning
of the evaluation phase
CVtp2
Non-adiabatic dissipation proportional to
Both inverting and non-inverting output available
42
Low-Power CMOS Logic Circuit
Topic Review
CAL Inverter
Cascades require single-phase clock and two
auxiliary square-wave clocks
PCK
o o
F1
CX F1
CX
F0
F0
43
Low-Power CMOS Logic Circuit
Topic Review
44
Low-Power CMOS Logic Circuit
Topic Review
Simulated switching energy-vs-frequency curves
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Low-Power CMOS Logic Circuit
Topic Review
46
