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# Low-frequency Capacitors

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```									                                                  ECE 304: Low-frequency Capacitors
Schematic
VP
15.00V
+

10.10mA          -
{VCC}                                                                           PARAMETERS:

0                         15.00V VP                   VP                              VCC = 15V        CBY = 100uF
10.00mA                                     CC = 50uF
100.0uA
RC = 1k          VB = {IC*(1+1/B_F)*RE+VBE}
RE = 100

+

+
{RB}               {RC}                                        RB = {B_F*(VCC-VB)/IC}
OUT          RS = 100
1.725V
100.0uA                          5.000V
R1                            B                  Q1
+              +                                     Qn                        PARAMETERS:         PARAMETERS:
+                     {RS}           {CC}
AC
Sweep   1V                                          -10.10mA                                      B_f = 100             VTH = 25.86418640mV
-
1.010V                  E                     I_S = 10fA            IC = 10mA
VBE = {Vth*LOG(IC/I_S)}
0                                                               {RE}               {CBY}

+
+
0
132.8KV
0

1A                           .model Qn NPN (Is={I_S}, Bf={B_F})
+

{RB}
0
FIGURE 1
CE amplifier with coupling and bypass capacitors; evaluator circuit shows value of RB

Gain and phase plots

50
CBY=100uF                                                          (460.54,45.86)
19.67dB
(10.00K,48.89dB)
25

0
(CC=5uF,3.816,16.54)

-25                                                                    (CC=50uF,331.44m,16.56)
(CC=1mF,16.38m,16.59)
-50
1.0mHz                       10mHz                100mHz            1.0Hz                 10Hz          100Hz           1.0KHz        10KHz
VDB(OUT)         16.5
Frequency

FIGURE 2
Gain vs. frequency for coupling capacitors CC = 1mF, 50µF and 5µf

-80

CC=5uF
-120                                                              CC=50uF

CC=1mF                                           (85.25,-110.96)
-160

CBY=100uF
-200
1.0mHz       10mHz                                 100mHz             1.0Hz                 10Hz            100Hz            1.0KHz        10KHz
P(V(OUT))                          -180      -135      -90
Frequency
FIGURE 3
Phase plots corresponding to Figure 2

Unpublished work © 10/19/2004 J R Brews Page 1                                                                                                   10/21/2004
NAME              Q_Q1
MODEL              Qn
IB              1.00E-04
IC              1.00E-02
VBE             7.15E-01
VBC            -3.28E+00
VCE             3.99E+00
GM              3.87E-01
RPI            2.59E+02
RX             0.00E+00
RO             1.00E+15
CBE            0.00E+00
CBC            0.00E+00
CJS            0.00E+00
BETAAC          1.00E+02
CBX/CBX2       0.00E+00
FT/FT2         6.15E+18
FIGURE 4
PSPICE output data

Interaction between CC and CBY
Although CBY dominates the low frequency corner frequency, when CC is made too small it
crowds CBY and raises the corner frequency. An example is shown in Figure 5 and Figure 6.

50

0
(CC=1mF,462.03,45.87)

(CC=1uF,903.83,45.89)

CBY=100uF
-50
100mHz               1.0Hz           10Hz              100Hz          1.0KHz            10KHz         100KHz
VDB(OUT)
Frequency
FIGURE 5
Gain plot for two cases; moving CC higher has almost doubled fL

-100

-150

CBY=100uF
-200
100mHz           1.0Hz               10Hz             100Hz         1.0KHz            10KHz         100KHz
P(V(OUT))   -180      -90
Frequency
FIGURE 6
Phase for same cases as Figure 5
The curves show the extreme cases where CC is large enough (1 mF) that it is a complete short-
circuit when CBY begins to be active, and the contrary case (CC =1µF) where both are active in
the same frequency region. A design that avoids interaction between CC and CBY (1 mF case)
uses a value of CC far too large to be practical. A better design than CC = 1 mF would increase
CBY to allow a lower value for CC and still obtain the same corner frequency of 462 Hz.

Unpublished work © 10/19/2004 J R Brews Page 2                                                     10/21/2004
If we assume that obtaining the minimum area for the capacitors is a design goal, a plot
like that in Figure 7 could be used to find the best value for CBY.
The existence of a minimum value for the total capacitance is argued as follows. At large
CBY the total capacitance increases almost linearly with CBY because CC is too small to matter.
Therefore, at large CBY the total capacitance increases as CBY increases. On the other hand, the
lowest value CBY can have is when CC is a short circuit, because CC then contributes nothing to
the corner frequency. To be a short-circuit, CC has to be infinity, so the total capacitance also is
infinity. Thus, as CBY drops towards its lowest value, the total capacitance heads for infinity.
Because the total capacitance increases as CBY goes up and also as CBY goes down, there has to
be a minimum in the total capacitance, as Figure 7 shows.

CBY+CC
fC=500Hz
CC
170                                                                    40
150
CBY+CC (uF)

30
130        121

CC (uF)
110                                                                    20
90
10
70
50                                                                  0
90   100      110       120          130        140         150
CBY (uF)
FIGURE 7
Plot of PSPICE results for total capacitance vs. CBY at a fixed corner frequency of 500 Hz
showing a minimum in the total capacitance of 111.6 µF near CBY = 103 µF and
CC = 8.6 µF; the labeled point is the 80%/20% heuristic design
Although we might want to use the true minimum-area design in a final product, when we
are thinking about the design in the early stages, we may not want to spend time to create such
plots for a lot of possibilities. To avoid making many plots, we can adopt the heuristic of the text
book and simply find CC and CBY using the approximation that CBY contributes 80% of fC and CC
contributes 20%. This choice is labeled in Figure 7 and, in this example, is a value within 10% of
the best choice. Once we have settled on the design we want, we can fine-tune by making a plot
like Figure 7 if it turns out that the design area is a critical factor.
Exercises
1. Construct Bode phase plots to correspond to CC = 1 mF and CBY = 100 µF in Figure 3. This
construction requires exact frequency expressions for the gain for the case when CC is a
short and CBY is active, and for the case when CBY is an open circuit and CC is active.
2. Assuming we want a low-frequency corner at fL = 500 Hz, select values for CBY and CC. Base
the design on the short-circuit time-constant estimate of the corner and assume CBY
contributes 80% of fC. Use the data in Figure 4. Check your results with PSPICE.

Unpublished work © 10/19/2004 J R Brews Page 3                                                       10/21/2004

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