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90nm RF CMOS technology for low-power 900MHz applications

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  • pg 1
									 A 90nm RF CMOS technology
supported by device modelling
   and circuit demonstrators
 J. Ramos, A. Mercha, W. Jeamsaksiri, D. Linten1,
  S. Jenei, S. Thijs, A.J. Scholten2, P. Wambacq1,
            I. Debusschere, S. Decoutere

                         IMEC Leuven, Belgium
        1   Also with the Vrije Universiteit Brussel, Belgium
             2Philips   Research Eindhoven, Netherlands
   Outline of the presentation

 Introduction
 Technology overview
 Active device description and modelling
 Passive devices description and modelling
 Circuit demonstrators results
 Conclusions
                       Introduction
   CMOS technology traditionally used for digital applications
  Aggressive Down-scaling for High-performance microprocessors

                     90nm ~ 3.6GHz
                     130nm ~ 1.5GHz           ↓ Lg            ↑ fT
                    180nm ~ 1GHz



        150GHz for a 90nm CMOS process *

   European IST IMPACT project
Pushing CMOS technology for its use in products operating
        well into the radio frequencies (5-20 GHz)
      Purely CMOS RF- Mixed-signal System-on-Chip
     * W. Jeamsaksiri et al. Symposium on VLSI Technology, June, 2004
       90nm CMOS technology*
 Active Device
 20W-cm P type Si substrate
 1.5nm EOT nitrided oxide dielectric
 5nm EOT Dual Gate Oxide device
 150nm poly gate stack
 Cobalt silicide
 5 Metal layer Cu back end of line
    * W. Jeamsaksiri et al. Symposium on VLSI Technology, June, 2004
        90nm RF CMOS technology

 Passive Devices
 Cu back end of line High-Q inductors
 High-Q MIM capacitors
 Junction varactors
 MOS-like accumulation-depletion varactors

  *S. Jenei et al. Topical Meeting on Silicon Monolithic Integrated Circuits, 2001
**G.J.Carchon et al., IEEE Trans. on Microwave Theory and Techniques, April 2004
              CMOS Transistor
                                                                        -5
                                                                  10
Digital key performances                                          10
                                                                        -6
                                                                                  Intrinsic Transistor
                                                                                      Performance

                                                                                   PMOS
                            NMOS




                                            [nA/mm]
                                                                        -7
                                                                  10                                   NMOS


                                                                        -8
                                                                  10




                                                      off
                                            I
                                                                                                              1.5nA/mm
                                                                        -9
                                                                  10
                                                                                                   720mA/mm
                                                                                 320mA/mm
                                                                       -10
                                                           10
                                                                             0     280        560 840 1120 1400
                                                                                              I [mA/mm]
                                                                                              on
                                                                       22
                                                                                       V         = 1.05 V
                                                                                          bias
                                                                       20




                                              Inverter delay,  [ps]
  Lphysical ~ 70nm                                                    18




                                                                d
                                                                                                   V       = 1.2 V
                                                                                                    bias

  Saturation Vt ~ 0.3V                                                16
                                                                                                             V       = 1.35 V
                                                                       14                                     bias
  Ion, NMOS=720mA/mm, Ion, PMOS=320mA/mm
                                                                                   Unloaded
                                                                       12
  Ioff, NMOS= Ioff, PMOS=1.5nA/mm                                               Ring oscillator              V
                                                                                                                 bias
                                                                                                                        = 1.5 V
                                                                       10
  ~15ps inverter delay                                                  30       40     50      60 70 80
                                                                                                 p*d [fJ]
                                                                                                                         90 100
                                          CMOS Transistor
        Analogue/RF key performances
                                                                                  Design specification:
                   30                                           250               fmax and fT > 5-10 times fapplication
                      moderate                   strong
                   25 inversion                inversion
            ds




                                                         200
(V-1) and g /g




                           g /I                  fmax
                                                                                     Moderate inversion


                                                                        f and f
                                                                      T
            m




                            m ds
                   20
                                                                150
                                                                                      Up to 5GHz applications.
                   15

                                                                      max
                                                    f
                          g /g                          T
                                                                                      Low power consumption.
                           m     ds                             100
                                                                        (GHz)
                   10
            m ds
    g /I




                                                                50                   Strong inversion
                    5

                    0                                           0                     Up to 20GHz applications.
                      0               1   2             3   4
                    10       10      10
                           Drain current, I
                                                    10
                                                   (mA/mm)
                                                           10                         Higher power consumption.
                                              ds



                        * W. Jeamsaksiri et al. Symposium on VLSI Technology, June, 2004
                                   ** J. Ramos et al. ESSDERC, September 2004
     CMOS Transistor modelling
 MOS Model requirements?
 Intrinsic model at any operation regime (Id–Vg, Chargers)

 First and higher order derivatives of Id (gm/Id, gm/gds,Distortion)

 Current noise (1/f , Thermal and Induced Gate noise)

 RF model (Impedance levels, current and power gains)

 Non Quasi static effects (High frequencies, large devices)

 Scalability (Freedom of design)
   CMOS Transistor modelling
MOS Model 11 – The choice
                                                             G
                                          Gate
                                        Resistance           RG
 All requirements fulfilled                                  Intrinsic Device
    Moderate inversion                  S                                 D
    Distortion                 Juncap                     MM11            Juncap
    Noise                                     Rjun,S       Rbulk        Rjun,D
    RF extension
    NQS                                                    Rsub Substrate
    Scalability                                 B                   Network
                                                            Cwell
                                                     SUB
    * R. van Langevelde et al. NanoTech 2002 - MSM, pag. 674-677 , April 2002
 CMOS Transistor modelling
MOS Model 11 – DC modelling
  Ldesign=100nm
  Wdesign=10mm                                              DC operation point
                                                            Moderate inversion




                                                            gm/Id and gm/gds
                                                            S-parameters Low
                                                           frequency points
                                                            Distortion

                  *Courtesy of Philips Research Laboratories
  CMOS Transistor modelling
MOS Model 11 – Analogue modelling
 Gate capacitance (accumulation to inversion, poly-depletion)
 Overlap capacitances (Bias dependent)
 Junction capacitance (STI-edge, gate-edge and bottom effects)




                   *Courtesy of Philips Research Laboratories
 CMOS Transistor modelling
NQS MOS Model 11 – S-Parameters




       fT
                  5-20 GHz range covered
               Passive Devices


 Passive device processed on standard 5LM Cu/Oxide BEOL.

 Provide circuit designers with a complete set of devices.

 In-house RF SPICE models.

 Alternative add-on solution for High-Q inductors
Metal Insulator Metal Capacitor
MIM Technology
                                                                      -12
                                                               5 10


                                                                      -12




                                        Capacitance, Cap (F)
                                                               4 10
                                                                                MIM Cap TaN + Oxide
                                                                                Target 1.1fF/mm2
                                                                      -12
                                                               3 10

                                                                                Y = M0 + M1*X
                                                                      -12       M0=0
                                                               2 10             M1=1.062e-15


                                                                      -12
                                                               1 10
                                                                                                   1.06 fF/mm2
                                                                       0
                                                                            0     500   1000    1500   2000   2500   3000   3500   4000

                                                                                                                     2
                                                                                          Capacitance area, A (mm )


                 Specific capacitance of 1.1fF/mm2
                 Embedded in Cu BEOL (M2- M3)
                 TaN plates (50-100 Ω/square)
                 35nm Silicon Oxide dielectric

*S. Jenei et al. Topical Meeting on Silicon Monolithic Integrated Circuits, 2001
 Metal Insulator Metal Capacitor
                                                      429fF MIM Capacitor
 MIM In-house RF Model
       Pass-through equivalent circuit




                              Coupling to
                               substrate
                                                           Lines  Models
                                                      Symbols  Measurement data


Q11=-Im(1/y11)/Re(1/y11)   Q22=-Im(1/y22)/Re(1/y22)          429fF (Optimized layout)


                                                               Q11
                                                       Q22
                                                            Q11
                                                      Q22
                                                            443fF
   Top plate grounded      Bottom plate grounded
Variable Capacitors - Varactors
Varactor Technology
   N+/Pwell and P+/Nwell Junction varactors
                                        1.3E-12

                                        1.2E-12

                                        1.1E-12
                                                          N+/Pwell




                                C (F)
                                        1.0E-12

                                        9.0E-13
                                                                              P+/Nwell
                                        8.0E-13

                                        7.0E-13
                                                  -1.00      -0.50     0.00       0.50   1.00
                                                                     Vbias (V)
   MOS-like accumulation-depletion varactor

          Poly - silicon
             oxide
     N+                    N+
            Nwell
Variable Capacitors - Varactors
Junction varactor In-house RF Model
   Pass-through equivalent circuit




 Linear passive components
 Spice diode models
 Frequency and bias dependent
Variable Capacitors - Varactors
MOS-like varactor In-house RF Model
   Pass-through equivalent circuit




 Linear passive components
 Frequency and bias dependent
        BEOL High Q Inductors
5 Level of Metal Cu/Oxide BEOL
                                                Outer
 IMD4
                                            G      S     G
                          Spiral
 IMD3                    Shunted                                Patterned
                         M4 & M5                                Poly or M1
 IMD2
                                                                  shield
 IMD1
                        Underpass
 PMD
                         Shunted
                                            G      S     G
                         M2 & M3
                                                Inner

         Conventional CMOS Cu/oxide BEOL
          High sheet resistance (35mW/square)
          Lossy substrate (20W-cm P type)
         *S. Jenei et al. Electron Device Letters, April 2002
       BEOL High Q Inductors
BEOL Inductors In-house RF Model




 Double lumped equivalent circuit to account for
distributed substrate coupling.
 Layout + process information used in closed form
calculation of the model parameters.
    *S. Jenei et al., IEEE Journal of Solid-State Circuits, January 2002
    BEOL High Q Inductors
BEOL Inductors In-house RF Model
    RF circuit demonstrators
Voltage-Controlled Oscillator (VCO)
                                Micrograph
  Schematic




                              • MIM Capacitors
                              • Junction Varactors
                              • BEOL High Q Inductors
                              • NMOS Transistors
    * D. Linten et al. Symposium on VLSI Circuits, June, 2004
     RF circuit demonstrators
Voltage-Controlled Oscillator (VCO)




Only possible with accurate device models and careful
                   circuit design!!!
             Conclusions
 A fully integrated RF CMOS technology
fabricated in a 90nm RF CMOS FEOL with High-
Q passive components processed on a
standard 5LM Cu/Oxide BEOL, has been
presented.

 Accurate modelling of the active a passive
devices made possible RF circuit design.

 RF CMOS can definitely become the
technology of choice for large volume RF
applications and Mixed-signal SoC platforms.
   Acknowledgments

                    IMEC P-line
          for processing the devices
                   Flemish IWT
              for financial support
          The European commission
in the framework of IST-2000-30016 IMPACT
           for the financial supports
    List of related publications
   W.Jeamsaksiri et al. “Integration of a 90nm RF CMOS technology (200GHz fmax -
    150GHz fT NMOS) demonstrated on a 5GHz LNA”, Symposium on VLSI Technology,
    June, 2004

   W.Jeamsaksiri et al. “Gate-source-drain architecture impact on DC and RF
    performance of sub-100-nm elevated source/drain NMOS transistors”, IEEE
    Transactions on Electron Devices, March, 2003

   M. Jurczak et al. “Elevated Co-silicide for sub-100nm High Performance and RF
    CMOS”, European Solid-State Device Research Conference, ESSDERC, September
    2002.

   V.C. Venezia et al. “The RF potential of high-performance 100nm CMOS
    technology”, European Solid-State Device Research Conference, ESSDERC,
    September 2002.

   D.Linten et al. “Low-power 5 GHz LNA and VCO in 90 nm RF CMOS”,
    Symposium on VLSI Circuits, June, 2004

   D.Linten et al. “A 5GHz fully integrated ESD-protected low-noise amplifier in
    90 nm RF CMOS”, Accepted for publication on the European Solid-State Circuits
    Conference, ESSCIRC, September 2004.
    List of related publications
   D.Linten et al. “A 328 mW 5 GHz voltage-controlled oscillator in 90 nm
    CMOS with high-quality thin-film post-processed inductor ”, Accepted for
    publication on the Custom Integrated Circuits Conference, CICC, October 2004.

   S. Thijs et al. “Implementation of Inductor Based ESD Protection for 5.5 GHz LNA
    in 90 nm RF CMOS – Concepts, constraints and Solutions”, Accepted for
    publication on the Electrical Overstress and Electrostatic Discharge Symposium,
    EOS/ESD, September 2004.

   D.Linten et al. “Influence of Back-End architecture on the performance of RF
    CMOS VCOs”, Southwest Symposium on Mixed-Signal Design, February 2003.

   D.Linten et al. “Design-driven optimisation of a 90 nm RF CMOS process by use of
    elevated source/drain”, European Solid-State Device Research Conference,
    ESSDERC, September 2003.

   S. Thijs et al. “Impact of Elevated Source Drain Architecture on ESD
    Protection Devices for a 90nm CMOS Technology Node”, Electrical
    Overstress and Electrostatic Discharge Symposium, EOS/ESD, September 2003.
   W.Jeamsaksiri et al. “Optimal frequency range selection for full C-V
    characterization above 45MHz for ultra thin (1.2-nm) nitrided oxide
    MOSFETs ”,       International Conference in Microelectronic Test Structures,
    ICMTS, March, 2004
    List of related publications
   M. Ferndahl et al. “40 and 60 GHz Frequency Doublers in 90-nm CMOS”,
    International Microwave Symposium, MTT-S, June 2004.
   M. Ferndahl et al. “The influence of the gate leakage current and the gate
    resistance on the noise and gain performances of 90-nm CMOS for micro and
    millimeter-wave frequencies ”, International Microwave Symposium, MTT-S, June
    2004.
   G.J. Garchon et al. “Wafer-Level Packaging Technology for High-Q On-Chip
    Inductors and Transmission Lines”, IEEE Transactions on Microwave Theory and
    Techniques, April 2004.

   G.J. Garchon et al. “High-Q above-IC inductors and transmission lines -
    comparison to Cu back-end performance”, Electronic Components and
    Technology Conference, ECTC, June 2004.

   G.J. Garchon et al. “Wafer-Level Packaging Technology for               Extended
    Global Wiring and Inductors”, European Solid-State Device               Research
    Conference, ESSDERC, September 2003.

   G.J. Garchon et al. “High-Q RF Inductors on standard Silicon realized using wafer-
    level packaging techniques”, International Microwave Symposium, MTT-S, June
    2003.
European IST IMPACT project
                          IMEC
                       Philips PITS


                        Technology
                       development
                          (WP3)




     Circuits design                  Devices modelling
         (WP1)                              (WP2)



                                            IMEC
         IMEC                         Philips Research
        Ericsson
   Chalmers University

								
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