Docstoc
EXCLUSIVE OFFER FOR DOCSTOC USERS
Try the all-new QuickBooks Online for FREE.  No credit card required.

8051-interfacing-techniques-pratical guide-with examples-in detail-part-5

Document Sample
8051-interfacing-techniques-pratical guide-with examples-in detail-part-5 Powered By Docstoc
					                A Robust UART Architecture Based on Recursive Running Sum Filter for
                                    Better Noise Performance

                              Himanshu Patel, Sanjay Trivedi, R. Neelkanthan, V. R. Gujraty
                     MSDG/MRSA, Space Applications Centre (ISRO), Ahmedabad-380 015 .Gujarat. INDIA .
                                  Email: {hnpatel,sanjay,rneel,vrg}@sac.isro.gov.in

                                      Abstract                           samples at receiver [5]. Serial receive data signal is
                                                                         directly sampled with system clock and samples are fed
                This paper describes a novel architecture of             to RRS filter. The window size of the filter is user
             Universal Asynchronous Receiver Transmitter (UART)          programmable and it decides baud rate.
             based on Recursive Running Sum (RRS) filter. UARTs             RRS filter hardware implementation is described in
             are used for asynchronous serial data communication         section-2. Window size selection criteria is described in
             between remote embedded systems. If physical channel        section-3. The UART Architecture is described in
             is noisy then, serial data bits get corrupted during        section-4 while section-5 gives simulation results and
             transmission. The robust UART core described here,          comparison with standard UART core. The robust
             utilizes recursive running sum filter to remove noisy       UART core described here is designed using VHDL
             samples. Input data signal is directly sampled with         and implemented on Xilinx Virtex FPGA .
             system clock and samples are accumulated over a
             window size. The window size is user programmable           2. RRS Filter Implementation
             and it should be set to one third of required bit period.
             The intermediate data bit is decoded using magnitude           The Recursive Running Sum (RRS) filter with
             comparator. A majority voter is used to decode actual       window size of M is described by following equations.
             data bit from three intermediate data bits. Comparison
             of MATLAB simulation results at different noise level                 1 − z -M
             shows that the robust UART described here has far              H(z) =
             better performance than standard UART at higher                       1 − z −1
             noise levels. Other advantage of this architecture is
                                                                            y(n) = x(n) + y(n-1) – x(n-M)
             that baud rate is decided by the window size so there
             is no need of any external “timer module” which is
                                                                             The hardware realization of the above equation is as
             normally required for standard UARTs. The robust
                                                                         shown in the Figure-1. It requires a Adder, subtracter, a
             UART core described here is designed using VHDL
                                                                         unit delay and a M samples delay element. The window
             and implemented on Xilinx Virtex FPGA.
                                                                         size (M) is related to baud rate which is user
                                                                         programmable. So M is variable, if a 16 bit register is
             1. Introduction                                             used to hold value of M, it can have values from 0 to
                                                                         65535. The hardware implementation of variable delay
                  Universal Asynchronous Receiver Transmitter            with above range would require 65535 D flip-flops and
             (UART) is used for asynchronous serial data                 large number of combinatorial logic for MUX and
             communication between remote embedded systems.              selection logic implementation. So this implementation
             Standard UART cores [1],[2],[3],[4] utilize three mid-bit   is not feasible for FPGA or ASIC platform.
             samples to decode the serial data bit and the sampling
             rate is derived from external timer module. But if the
             physical channel is noisy then data bits get corrupted
             during transmission and it leads to wrong data
             decoding at receiver.
                 To overcome the noise problem a digital low pass
             filter based architecture is proposed in this paper.              Figure-1 Hardware realization of RRS filter
             Recursive Running Sum (RRS) is simple low pass filter,
             it can be used to remove noise samples from data




20th International Conference on VLSI Design (VLSID'07)
0-7695-2762-0/07 $20.00 © 2007
                 The Other approach for hardware realization of RRS
             filter using a factor of M decimator is shown in Figure-
             2. It requires a Adder, subtracter, two unit delays and a
             down sampler of factor M. The implementation of down
             sampler requires a 16 bit counter and a magnitude
             comparator which is much simpler than previous
             approach. So this approach is selected for robust              Figure-4: Window offset when M = bit_period/3
             UART implementation.
                                                                            For this case, different scenarios of offset between
                                                                         window and start bit is shown in the figure-4. So three
                                                                         samples are available in a bit period. In the worst case
                                                                         also two full windows are available in one bit period so
                                                                         two out of three samples are correct, so bit will be
                                                                         correctly decoded by the majority voter. Thus window
                   Figure-2: Implementation of RRS using down            size equal to one third of bit period is optimum
                                   sampler                               selection.
             3. Window Size Determination
                The selection of window size (down sampling factor-      4. UART Architecture
             M) is important for correct data decoding. The input
             data signal (rxd_in) is sampled at system clock and fed        The architecture of UART receiver is shown in the
             to RRS filter as input x(n), output data samples y(n) are   figure-5. The incoming rxd_in signal is sampled at
             available at the interval of M samples because of the       system clock. These one bit samples are padded with
             down sampler. For application of the above filter in the    zeros and made a 16 bit number x(n). It is fed to
             asynchronous communication where data bits are              recursive running sum filter with window size equal to
             transmitted asynchronously, the offset between              one third of bit period. The output of RRS filter is a 16
             window and start bit is important. When the window                                                      h
                                                                         bit value which is number of ones in t e window
             size (down sampling factor- M) is equal to bit period,      duration. It is fed to magnitude comparator, where it is
             different scenarios of offset between window and start      compared with M/2, if the value is greater than M/2
             bit is shown in the figure-3.                               then the window samples (intermediate data bit) is
                                                                         decoded as ‘1’ otherwise ‘0’. Thus 16 bit value is
                                                                         converted back to 1 bit.
                                                                                                         M −1
                                                                                                                           M
                                                                            rxd_int(n) = ‘1’ when        ∑ x(n − k ) ≥     2
                                                                                                         k=0
                                                                                             ‘0’ otherwise.
                                                                         This intermediate data bit is fed to 3 stage shift register.
                                                                         These 3 bits are used to detect start bit and they are
                   Figure-3 : Window offset when M = bit_period          also fed to majority voter for data bit and stop bit
                                                                         decoding.
                The offset between window and start bit can vary            The further process is similar to standard UART,
             from 0 to M/2. In the worst case offset of M/2, half of     there is a 8 bit shift register to hold the data byte and
             the samples in current window are from previous bit         the finite state machine generates control signals for
             and remaining half samples are from current bit, so this    the shift register and other modules. Transmission from
             will lead to wrong decoding of the data bits.               the UART is similar to standard UART, using a shift
                                                                         register. The baud rate for serial communication is
                To overcome above problem the window size should         decided by the window size (M), so there is no need of
             be chosen smaller than bit period so that multiple          any external timer for baud rate generation unlike
             windows are available in one bit period. Odd number of      standard UART. The baud rate equation is as follows.
             windows should be chosen in one bit period so that a                              clock _ freq
             majority voter can be used to decode a bit from the odd        Baud _ rate =
             number of the samples. From above considerations a                                   M *3
             factor of 3 is chosen so that 3 windows are available in           Where, clock_freq is system clock frequency,
             one bit period.                                                           M is window size, (1 to 216)




20th International Conference on VLSI Design (VLSID'07)
0-7695-2762-0/07 $20.00 © 2007
                                                          Figure-5: Architecture of robust UART

             5. Results                                                      7(a) shows transmitted serial data, figure-7(b) shows
                The UART core described here has been designed               serial data with AWGN noise, figure-7(c) shows serial
             using VHDL. Noise insertion is done using MATLAB®               data samples at receiver, these samples are written in a
             program. The core has been simulated using                      text file and give as input to VHDL test bench. The
             ModeSim® while hardware implementation is done on               UART is instantiated in testbench and serial data
             Xilinx Virtex FPGA.                                             samples from the text file is fed to input rxd_in. The
                                                                             output bytes from UART is written in a text file. Figure -
             5.1 Test Methodology                                            8 shows Modelsim® simulation waveform, rxd is input
                                                                             serial data which contains lot of noise while
                                                                             rxd_bit_decode is output of majority voter and
                                                                             sbuf_rx_reg is 8 bit data output.

                                                                             5.2 Comparison with standard UART

                                                                                 The Comparison of robust UART described here
                                                                             with standard UART (Synopsys® DesignWare
                                                                             DW8051 internal UART [2]) is done at different noise
                                                                             levels using the test methodology described in earlier
                                                                             section, the results are shown in table 1 and
                                                                             corresponding graph is shown in figure-9. The x axis of
                                                                             graph shows ratio of correctly received data bytes and
                                                                             total transmitted bytes in percentage. The y-axis of the
                                                                             graph is percentage of average corrupted samples in a
                             Figure-6: Test Methodology                      bit period. It should be noted that it is impossible to
                                                                             recover data bits if more than 50% of data samples in a
                 The test methodology is described in the figure 6,          bit period are corrupted by noise.
             Serial data to be transmitted to UART is written in a text
             file. Typically randomly generated few thousand data                The performance of standard UART deteriorates if
             bytes are written in the text file. A MATLAB® program           more than 6% of data samples are corrupted in a bit
             converts parallel bytes to serial and adds start and stop       period, while for robust UART the performance
             bit, it also adds AWGN (Additive White Gaussian                 deteriorates only after 37%. Thus comparison Graph
             Noise) at different SNR (Signal to Noise Ratio) level.          shows that robust UART has better performance than
             Figure 7 shows MATLAB® simulation results, figure -             standard UART at higher noise levels.




20th International Conference on VLSI Design (VLSID'07)
0-7695-2762-0/07 $20.00 © 2007
                                               Figure-7: Plot of serial data with noise & data samples




                                                      Figure-8: ModelSim simulation waveform




                   Table- 1: Comparison with standard UART at
                              different noise levels
                                                                                          Figure-9: Graph of table-1




20th International Conference on VLSI Design (VLSID'07)
0-7695-2762-0/07 $20.00 © 2007
             5.3 FPGA Implementation                                               7. References
                  The robust UART described in this paper has been                 [1] Intel® MCS-51 microcontroller family user’s manual
             implemented on xilinx® virtex XCV300 FPGA [9]. The                    from www.intel.com
             synthesis report is as shown below, it consumes only
             159 virtex slices, thus UART core occupies very small                 [2] Synopsys DesignWare® DW8051 MacroCell databook
             area.                                                                 from www.synopsys.com
             --------------------------------------------------------------
             Selected Device : v300pq240-4                                          [3] Liakot Ali, Roslina Sidek, Ishak Aris, Alauddin Mohd.
              Number of Slices:                   159 of 3072                5%    Ali, and Bambang Sunaryo Suparjo “Design of a micro-
              Number of Slice Flip Flops: 192 out of 6144 3%                       UART for SoC application” Computers & Electrical
              Number of 4 input LUTs: 241 out of 6144 3%                           Engineering Journal, Elsevier Publ. Volume 30, Issue 4 , June
              Number of bonded IOBs: 25 out of 170                           14%   2004, Pages 257-268
              Number of GCLKs:                    1 out of 4                25%
             ------------------------------------------------------------------    [4] Norhuzaimin, J. Maimun, H.H. “The design of high
                                                                                   speed UART” Asia-Pacific Conference on Applied
             6. Conclusion                                                         Electromagnetics (APACE 2005). Dec. 2005

                  This paper describes a robust UART architecture                  [5] Yong Lian Poh Choo Ho “ECG noise reduction using
             based on recursive running sum filter for removal of                  multiplier-free FIR digital filters” 7th International
             channel induced noise. The baud rate of serial                        Conference on Signal Processing (ICSP ‘04.) 2004. Volume: 3
             communication is decided by the window size of the                    pages: 2198 - 2201
             filter, which is user programmable and should be set to
             one third of required bit period. Thus it does not require            [6] M. Delvai, U. Eisenmann, W. Elmenreich, “Intelligent
             any external module for baud rate generation.                         UART Module for Real-Time Applications” First Workshop
             Comparison of simulation results shows that the                       on Intelligent Solutions in Embedded Systems (WISES),
             performance of standard UART deteriorates if more                     pages 177-185, Vienna, Austria, June 2002
             than 6% of data samples are corrupted in a bit period
             while for robust UART the performance deteriorates                    [7] P.J. Ashenden, “The Designer’s guide to VHDL”, Morgan
             only after 37% thus the robust UART has far better                    Kaufmann Publ., 2000
             performance than standard UART at higher noise
             levels.                                                               [8] Mitra, S. K., “Digital Signal Processing - A computer
                                                                                   based approach,” Tata McGraw-Hill, 2001

                                                                                   [9] Xilinx® Virtex FPGA datasheets from www.xilinx.com




20th International Conference on VLSI Design (VLSID'07)
0-7695-2762-0/07 $20.00 © 2007

				
DOCUMENT INFO
Description: this gives detail flow of interfacing of 8051 with other equipments or modules and different techniques to interface a good book for pratical exposure