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The CORDIC
Algorithm
By
Mohammad Kharashgeh
Hardik Jambusaria
Wei-Li Chen
Donald Guelich
CORDIC
• Acronym for Coordinate Rotations
Digital Computer.
• First designed in 1950s
• Computes trigonometric and some other
special functions.
CORDIC idea
CORDIC trick
x(i+1) = x(i) * cos α - y(i) * sin α
y(i+1) = y(i) * cos α + x(i) * sin α
• x’(i+1) = x(i) - y(i) * tan α
• y’(i+1) = y(i) + x(i) * tan α
• Choose angles that has tan powers of 2
Forming angles
• We use these angles to form all other
angles 45, 26.6, 14, 7.1, 3.6, 1.8, .9, 0.4
• 30 = 45 -26.6+14 -7.1+3.6+1.8 -0.9+0.4
• 90 = 45+26.6+14+7.1-3.6+1.8 -0.9+0.4
Project Objectives
• Going through the whole process of
project design: from specification to
silicon!
• More experience in using tools
• More experience in using VHDL
• Group work
Schedule
• 10th March: CORDIC specification
• 23rd March: Component designs
• 28th March: State machine design
• 3rd April: System simulation and testing
-----------------------------------------------------
• 20th April: Synthesizing CORDIC
• 25th April: Post vs. Pre Synthesis simulation.
• 1st May: Power and timing optimizations
• 8th May: Layout and refinement
Top level diagram
Fixed point representation
Block
Diagram
Main Components
• Two shifters
• A lookup table
• Two 9bit adders
• A 16bit adder
VHDL Components
COMPONENT shifter IS
PORT( abc :IN STD_LOGIC_VECTOR( 2 DOWNTO 0);
data_shi :IN STD_LOGIC_VECTOR( 8 DOWNTO 0 );
data_out :OUTSTD_LOGIC_VECTOR( 8 DOWNTO 0 ));
END COMPONENT;
COMPONENT lookuptable IS
PORT( address :IN STD_LOGIC_VECTOR( 2 DOWNTO 0 );
data :OUT STD_LOGIC_VECTOR( 15 DOWNTO 0 ));
END COMPONENT;
COMPONENT adder9bit IS
PORT( operand1 :IN STD_LOGIC_VECTOR( 8 DOWNTO 0 );
operand2 :IN STD_LOGIC_VECTOR( 8 DOWNTO 0 );
operation :IN STD_LOGIC;
result :OUT STD_LOGIC_VECTOR( 8 DOWNTO 0 ));
END COMPONENT;
COMPONENT adder16bit IS
PORT( operand1 :IN STD_LOGIC_VECTOR( 15 DOWNTO 0 );
operand2 :IN STD_LOGIC_VECTOR( 15 DOWNTO 0 );
operation :IN STD_LOGIC;
result :OUT STD_LOGIC_VECTOR( 15 DOWNTO 0 ));
END COMPONENT;
Lookup table for CORDIC
Address Angle
0 45.0000
1 26.5650
2 14.0362
3 7.1250
4 3.5763
5 1.7899
6 0.8951
7 0.4476
Lookup table code
Architecture design OF lookup IS
BEGIN
PROCESS(address)
BEGIN
CASE address IS
WHEN "000" => data <= "0010110100000000";
WHEN "001" => data <= "0001101010011000";
WHEN "010" => data <= "0000111000000000";
WHEN "011" => data <= "0000011100011000";
WHEN "100" => data <= "0000001110011000";
WHEN "101" => data <= "0000000111001000";
WHEN "110" => data <= "0000000011101000";
WHEN "111" => data <= "0000000001101000";
WHEN OTHERS => data <=
"0000000000000000";
END CASE;
END PROCESS;
END design;
Lookup simulation
Shifter specification
• Always shifts right
• Variable length
• Parallel (shifting by 1 or 7 takes same
time)
• Sign extension
Shifter dataflow schematic
Shifter simulation
Shifter synthesis
Adders specification
• Two size of adders used (9 and 16 bits)
• An input signal determines addition or
subtraction
Adder/ subtractor 9bit
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY adder9 IS
PORT( operand1, operand2 :IN STD_LOGIC_VECTOR( 8 DOWNTO 0 );
operation :IN STD_LOGIC;
result :OUT STD_LOGIC_VECTOR( 8 DOWNTO 0 ));
END adder9;
ARCHITECTURE a9 OF adder9 IS
BEGIN
PROCESS( operand1, operand2, operation )
BEGIN
IF operation = '0' THEN
result <= operand1 + operand2;
ELSIF operation = '1' THEN
result <= operand1 - operand2;
ELSE NULL;
END IF;
END PROCESS;
END a9;
Adder9 simulation
adder16
• Same design as adder9
• Used for angle (addition / subtraction)
System operation
• The asynchronous reset is used to initialize the system.
When the reset is asserted:
– Internal signals x and y are set to initial values.
• X <= 010011011
• Y <= 000000000
– Internal signal z is set to the input angle.
• Upon rising edge of clock
– For the first 7 clock cycles, the CORDIC algorithm executes.
– For the 8th clock cycle, the sin and cos outputs are updated.
State Machine Code
PROCESS( clock, reset )
BEGIN
IF reset = '1' THEN
x <= "010011011";
y <= "000000000";
z <= angle;
count <= "0000";
ELSIF clock'EVENT AND clock = '1' THEN
IF count = "1000" THEN
cos <= x;
sin <= y;
ELSE
x <= x_out2;
y <= y_out2;
z <= z_out2;
count <= count + 1;
END IF;
END IF;
END PROCESS;
System Timing
• The shifter requires 8 clock cycles to before the CORDIC can
update sin and cos.
1 2 3 4 5 6 7 8
clock
reset
sin
cos
Frequency
• The simulation was run at 20 MHz to
check for functional correctness.
• In order to increase the speed of the chip,
we’ve chosen parallel I/O between the
functional blocks.
Simulation
• Input:
angle = 00011110 00000000 = 30
• Outputs:
sin (angle) = 010000000 = 0.5
cos (angle) = 011011111 = 0.87109375
Error analysis
• Two types of error:
– Error from representing the angle discretely
Since we form the angle from adding and subtracting 8
other angles, some error will be introduced.
– Error in sine and cosine
Since Our CORDIC algorithm uses 8 iterations to compute
sine and cosine and for that it uses 8 bit fraction precision.
From our initial simulation, the error is shown as:
Error = Sim – Actual * 100% = 0.87109375 – 0.866025404 *100%= 0.005852%
Actual 0.866025404
Future Work
• Increase precision
• Synthesis of the whole chip
• Post synthesis simulation and testing
• Optimize speed and area
• improving power scheme
• Layout and design refinement
References
[1] Ray Andraka. A survey of CORDIC
algorithms for FPGA based Computers.
[2] Behrooz Parhami. Computer
Arithmetic: algorithms and Hardware
design.
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