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Method Of Maintaining The State Of Semiconductor Memory Having Electrically Floating Body Transistor - Patent 8130547

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Method Of Maintaining The State Of Semiconductor Memory Having Electrically Floating Body Transistor - Patent 8130547 Powered By Docstoc
					
				
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Description: The present invention relates to semiconductor memory technology. More specifically, the present invention relates to methods of maintaining the state of semiconductor memory device/array of devices having an electrically floating bodytransistor.BACKGROUND OF THE INVENTION Semiconductor memory devices are used extensively to store data. Static and Dynamic Random Access Memory (SRAM and DRAM, respectively) are widely used in many applications. SRAM typically consists of six transistors and hence has a large cellsize. However, unlike DRAM, it does not require periodic refresh operations to maintain its memory state. Conventional DRAM cells consist of a one-transistor and one-capacitor (1T/1C) structure. As the 1T/1C memory cell feature is being scaled,difficulties arise due to the necessity of maintaining the capacitance value. DRAM based on the electrically floating body effect has been proposed (see for example "A Capacitor-less 1T-DRAM Cell", S. Okhonin et al., pp. 85-87, IEEE Electron Device Letters, vol. 23, no. 2, February 2002 and "Memory Design UsingOne-Transistor Gain Cell on SOI", T. Ohsawa et al., pp. 152-153, Tech. Digest, 2002 IEEE International Solid-State Circuits Conference, February 2002). Such memory eliminates the capacitor used in the conventional 1T/1C memory cell, and thus is easierto scale to smaller feature size. In addition, such memory allows for a smaller cell size compared to the conventional 1T/1C memory cell. However, unlike SRAM, such DRAM memory cell still requires refresh operation, since the stored charge leaks overtime. A conventional 1T/1C DRAM refresh operation involves first reading the state of the memory cell, followed by re-writing the memory cell with the same data. Thus this read-then-write refresh requires two operations: read and write. The memorycell cannot be accessed while being refreshed. An "automatic refresh" method", which does not require first reading the memory cell state, has been described in Faza