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Input Output of Memory

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This article will show us how to examine the memory map Input / Output (I/O) and isolated I/O. After that, examine the motorola 68230 PI/T Chip. Next, the I/P interfacing circuits

More Info
									      Input/Output


Some Fundamental Stuff …




           Microprocessor   1
Objectives

 Examine memory map I/O and
 isolated I/O
 Examine the Motorola 68230 PI/T
 chip
 Interfacing circuits




             Microprocessor        2
Outcomes

 To be able to explain the difference
 between memory map I/O and
 isolated I/O
 To be able to program the 68230
 PI/T
 To be able to interface LEDs and
 switches to the 68230



             Microprocessor             3
      Memory Mapped I/O
For each I/O device or interface:
• A number of registers can be
  accessed by the CPU
• Each of the registers is given a
  unique address.
• The address decoder enables the
  device to recognize its addresses
  when issued by CPU.


 Addresses of control, data direction and data registers in I/O
 devices or interfaces are treated by the CPU as if they were
 conventional memory locations or addresses:
   Hence the same instructions that move data to or from
   memory can be used to transfer data to or from I/O devices.
                            Microprocessor                        4
  Isolated I/O
I/O devices do not share the same
memory map.
It has its own map – I/O map

                    •Separate input and
                    output instructions e.g.
                    IN, OUT




               Microprocessor                  5
Difference between Memory mapped
          and Isolated I/O


  In the Isolated scheme, IN, OUT, INS
  and OUTS instructions are required.
  In the Memory-mapped scheme, any
  instruction that references memory
  can be used.




              Microprocessor         6
Flight 68K Memory Map




                 Microprocessor   7
  68000 Memory Mapped I/O
  The Motorola 68000 uses memory mapped I/O, where
  device registers are assigned unique addresses within
  the memory address space. I/O data and control
  registers are treated as if they were memory locations.

Example: The Filte 68K board includes:
    Two parallel ports A, B using the Motorola 68230
    Parallel Interface/Timer (PI/T) chip, with a
    Port General Control Register (PgCR) $800001




                        Microprocessor                  8
68230 PI/T Structure




                Microprocessor   9
Parallel data port has the following
addresses:

Parallel data port A (or PA)
  PADR, Data Register of port A,            $800011
  PADDR, Data Direction Register of port A, $800005
  PACR, Port A Control Register,            $80000D


Parallel data port B (or PB)
  PBDR, Data Register of port B,            $800013
  PBDDR, Data Direction Register of port B, $800007
  PBCR, Port B Control Register,            $80000F



                     Microprocessor                   10
The Motorola 68230 PI/T

Contains three 8-bit parallel ports: PA, PB & PC
PA & PB can be programmed as input or output
ports, or as both at the same time (full-duplex
operation).
Can be programmed to interrupt the processor
when any port receives new data.
68230 also contains a programmable 24 bit
counter.




                   Microprocessor              11
     …/ cont. 68230 PI/T
Handshaking lines can be programmed to provide
different communications protocols to the I/O
device.
The 68230 is programmed, and data transfers take
place using a total of 23 internal 8-bit registers.




                     Microprocessor              12
        68230 (PI/T) Registers

                   Port General Control Register
                                                   $800001

PortA Control Register                            PortB Control Register

                            $80000D         $80000F

PortA Data Direction Register                     PortB Data Direction Register

                            $800005          $800007

PortA Data Register                               PortB Data Register
                            $800011          $800013



  PA7                 PA0                              PB7              PB0
                                 Microprocessor                               13
Flight 68K Memory Map


 Parallel data port A
   PADR, $800011
   PADDR, $800005
   PACR, $80000D


 Parallel data port B
   PBDR,  $800013
   PBDDR, $800007
   PBCR,  $80000F



                        Microprocessor   14
68230 Register Addresses
REGISTER                                        ADDRESS OFFSET
Port General Control Register             PGCR  $800001  $00
Port Service Request Register             PSRR  $800003  $02
Port A Data Direction Register            PADDR $800005  $04
Port B Data Direction Register            PBDDR $800007  $06
Port C Data Direction Register            PCDDR $800009  $08
Port Interrupt Vector Register            PIVR  $80000E  $OA
Port A Control Register                   PACR  $80000D  $OC
Port B Control Register                   PBCR  $80000F  $OE
Port A Data Register                      PADR  $800011  $10
Port B Data Register                      PBDR  $800013  $12
Port A Alternate Register                 P AAR $8000 15 $14
Port B Alternate Register                 PBAR  $800017  $16
Port C Data Register                      PCDR  $800019  $18
Port Status Register                      PSR   $80001E  $IA
Timer Control Register                    TCR   $800021  $20
Timer Interrupt Vector Reg.               TIVR  $800023  $22
Counter Preload Reg. High                 CPRH  $800027  $26
Counter Preload Reg. Middle               CPRM  $800029  $28
Counter Preload Reg. Low                  CPRL  $80002E  $2A
Count Register High                       CNTRH $80002F  $2E
Count Register Middle                     CNTRM $800031  $30
Count Register Low                        CNTRL $800033  $32
Timer Status Register            Microprocessor
                                          TSR   $800035  $34     15
Microprocessor   16
   Programming The 68230

Ports A and B are capable of operating in one
of four possible modes programmed using the
two msb’s of PGCR:
  Mode   0   Unidirectional 8 bit transfers
  Mode   1   Unidirectional 16 bit transfers.
  Mode   2   Bidirectional 8 bit transfers.
  Mode   3   Bidirectional 16 bit transfers.




                        Microprocessor          17
    Port General Control Register
                  0                                            0        Hex


    7         6            5         4          3         2        1         0

    0         0         0            0           0         0        0         0




0       0   Mode   0   Disable
0       1   Mode   1   Handshaking               •    Control the sense of the
1       0   Mode   2                                  handshaking
1       1   Mode   3   0       Disable
                       1       Enable

            Move.b #$00,PgCR             ;Set port to general mode

                                     Microprocessor                               18
Within each of these modes are sub modes programmed
using PACR and PBCR:
  00     Double-buffered input, single buffered output.
  01     Double buffered output, no latching of inputs.
  1X     Input unlatched, No buffering of output.
Each of the three ports has a Data Direction Register
(DDRA, DDRB and DDRC) associated with it:
  Each bit in the DDR controls the direction of I/O on the
  corresponding bit on the port (1 for output and 0 for input).
  e.g. DDRA = $00 for input $FF for output.



                           Microprocessor                         19
 Port A/B Control Register
             8                               0       Hex

 7       6       5      4          3     2       1         0

 1       0       0      0           0    0       0         0



Submode 00
Submode 01
Submode 1X
     Commonly used mode is: Mode 0, Submode 1X
                                  0
           Simple I/O in both directions
     Move.b #$80,PaCR   ;Set portA to submode IX


                        Microprocessor                         20
Microprocessor   21
Port A/B Data Dirction Register
            F                                0       Hex

7       6       5       4          3     2       1         0

1       1       1       1           0    0       0         0




                 1 – output
                 0 – input
Move.b #$F0,PaDDR ;Set half of portA input and half output



                        Microprocessor                         22
Microprocessor   23
  Accessing the 68230 Registers (1)
 Method 1
        ORG $400400                        ;Start Address
Start   Movea.l #$800001,A0                ;Base address of PI/T
        Move.b #$00,A0                     ;Set port to general mode
        Move.b #$80,+$0E(A0)               ;Set PortB to mode 1X
        Move.b #$FF,+$06(A0)               ;Set PortB to output
        Move.b #$01,+$12(A0)               ;send $01 to output

Reminder:
Port General Control Register     PGCR            $800001              $00
Port B Control Register           PBCR            $80000F              $OE
Port B Data Direction Register    PBDDR           $800007              $06
Port B Data Register              PBDR            $800013              $12

                          Microprocessor                               24
  Accessing the 68230 Registers (2)
Method 2
***************** Declarations ****************
PgCR         equ $800001 ;Port general control register
PbDDR        equ $800007 ;PortB data direction register
PbCR         equ $80000F ;PortB control register
PbDR         equ $800013 ;PortB data register



      Org   $400400        ;Start Address
Start Move.b #$00, PgCR    ;Set port to general mode
      Move.b #$80, PbCR    ;Set PortB to mode 1X
      Move.b #$FF, PbDDR   ;Set PortB to output
      Move.b #$01, PbDR    ;send $01 to output


                       Microprocessor                  25
        D0   Leds

PortB


        D7



               Microprocessor   26
 SAQ
What is the effect of loading the value
$55 into port A data direction register
of the Motorola PI/T?




               Microprocessor             27
    Difference between IDE68K and
    Flight 68K
            org $400                         PGCR   EQU     $800001
Switches    equ $00E001                      PADR   EQU     $800011
Leds        equ $00E003                      PADDR  EQU     $800005
Here        Move.b Switches,D0               PACR   EQU     $80000D
            Move.b D0,Leds                   PBDR   EQU     $800013
            Bra Here                         PBDDR  EQU     $800007
                                             PBCR   EQU     $80000F
                                             *Initialize PI/T
                                             INIT   MOVE.B #$00,PGCR
                                                    MOVE.B #$80,PACR
                                                    MOVE.B #$00,PADDR
                                                    MOVE.B #$80,PBCR
                                                    MOVE.B #$FF,PBDDR
                                                    MOVE.B #$00,PBDR
                                             *Main routine
                                             READ   MOVE.B PADR,D0
                                                    MOVE.B D0,PBDR
           IDE68K                                   BRA     READ
                                                  Flight 68K
                                 Microprocessor                         28
***************** Declarations ****************
PgCR        equ $800001    ;Port general control register
PbDDR       equ $800007    ;PortB data direction register
PbCR        equ $80000f    ;PortB control register
PbDR        equ $800013    ;PortB data register

***************** Main Program ****************

           Org $400400            ;Start address

Start      Move.b   #$00,PgCR     ;Set port to general mode
           Move.b   #$80,PbCR     ;Set portB to submode IX
           Move.b   #$ff,PbDDR    ;Set portB to output
           Move.b   #$01,PbDR     ;Send $01 to output


                          Microprocessor                  29
******************** Declarations ******************
PgCR         equ $800001 ;Port general control register
PaDDR        equ $800005 ;PortA data direction register
PaCR         equ $80000d ;PortA control register
PaDR         equ $800011 ;PortA data register

***************** Main Program *********************
             Org $400400          ;Start address
Start        Move.b #$00,PgCR     ;Set port to general mode
             Move.b #$80,PaCR     ;Set portA to submode IX
             Move.b #$ff,PaDDR    ;Set portA to output
Again        Move.b #$01,PaDR     ;Send $01 to output
             Bsr    Delay         ;Call delay routine
             Move.b #$00,PaDR     ;Send $00 to output
             Bsr    Delay         ;Call delay routine
             Bra    Again         ;repeat

***************** Subroutine ***********************
Delay        Move.l #250000,d1
Here         subq.l #1,d1
             Bne    Here
             Rts
                           Microprocessor                     30
                 move.l #250000,D1


           * subq.l #1,D1



                 bne *




Microprocessor                       31

								
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