Circuits by roshan.iesl

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									  Computer
Fundamentals
Lecture 10: Logic Circuits
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   Objectives
      After completing this module you will be
       able to:
            Understand Sequential Circuits
                  SR, JK, D, T Flip-flops, Master-Slave Flip-Flops




Computer Fundamentals (101)     Lecture 06 - Logic & Control - Part III   © Sri Lanka Institute of Information Technology
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   Lecture Outline
      Sequential Circuits (Fundamental Building Blocks
       of Memory)
            Introduction to Latch and Flip-Flops




Computer Fundamentals (101)   Lecture 06 - Logic & Control - Part III   © Sri Lanka Institute of Information Technology
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                      Sequential Circuits
      So far we have seen the combinational logics
            Output(s) can depend only on the current value of the input
             variables.
      Here we will look at Sequential Logic circuits
            the output(s) can depend on present inputs and also past
             values of the input (output state).
      Sequential circuits exist in one of a defined
       number of states at any one time
            they move "sequentially" through a defined sequence of
             transitions from one state to the next
            The output variables are used to describe the state of a
             sequential circuit either directly or by deriving state
             variables from them.
Computer Fundamentals (101)   Lecture 06 - Logic & Control - Part III   © Sri Lanka Institute of Information Technology
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   Sequential Circuits




                               Input
                                                 Combinational
                                                    Circuit                                          Output

                                                                             Flip-Flops

                                                                         Clock




Computer Fundamentals (101)   Lecture 06 - Logic & Control - Part III   © Sri Lanka Institute of Information Technology
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     Sequential Circuits
 n   Sequential Circuit Design Procedure                                                        1. The Problem is stated
        Recall Combinational Circuit Design                                                    2. I/O variables are assigned
                                                                                                3. Truth table(I/O relation)
        Sequential Circuit: State diagram, State table                                         4. Simplified Boolean Function
        F/F : 2m+n (m - State , n - Input )                                                    5. Logic circuit diagram




                                          SET
        x                             J         Q    A

                                      K   CLR
                                                Q
                                                                                 Logic Diagram


                                          SET
                                      J         Q    B

                                      K   CLR
                                                Q

                              Clock

Computer Fundamentals (101)           Lecture 06 - Logic & Control - Part III        © Sri Lanka Institute of Information Technology
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                Basic Storage Elements
                  (Latch or Flip-Flop)
    A flip-flop or latch is a circuit that has two stable
       states and can be used to store state
       information.
      This circuit can be made to change state by
       signals applied to one or more control inputs and
       will have one or two outputs
      Flip-flops are the fundamental element of
       sequential circuits.
            (gates are the fundamental element for combinational
             circuits)
      Flip-flops is a binary cell capable of storing one
       bit information and basic storage element in
       sequential logic
Computer Fundamentals (101)   Lecture 06 - Logic & Control - Part III   © Sri Lanka Institute of Information Technology
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   Flip-Flops
      Flip-flops have two outputs
            One for the normal value (Q)
            One for the complement value the bit stored it (Q).
      Flip-flops can be either simple (transparent or
       asynchronous) or clocked (synchronous)
      the transparent ones are commonly called latches.
       [The word latch is mainly used for storage
       elements]
      The clocked devices are described as flip-flops.




Computer Fundamentals (101)   Lecture 06 - Logic & Control - Part III   © Sri Lanka Institute of Information Technology
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   Flip-Flops(Contd.)
      Usage: Flip-flops and latches are a fundamental
       building block of digital electronics systems used
       in computers, communications, and many other
       types of systems.

      Main types of flip-flops
        S-R(Set-Reset) Flip-Flop
        D (Data or Delay) Flip Flop
        J-K Flip-Flop




Computer Fundamentals (101)   Lecture 06 - Logic & Control - Part III   © Sri Lanka Institute of Information Technology
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                Basic Storage Elements
                    (SR NOR latch)
                                                                            A
                                                                            B
                                                                            A                             F = A+B
                                                                            B
                                                                                    NOR Gate

                                                                                    Truth table for NOR
                              0                                                             gate
If S = 1, R = 0 , Q = 1, Q = 0                                                     0          0              1
                                                                                   0          1              0
If S = 0, R = 0 ,,Q = 1, Q = 0
 If S = 0, R = 0 Q = 1, Q = 0                                                      1          0              0
                                                                                   1          1              0
If S = 0, R = 1 , Q = 0, Q = 1
                                                                                Memory
If S = 0, R = 00, ,Q = 0, Q = 11
 If S = 0, R =      Q = 0, Q =


Computer Fundamentals (101)       Lecture 06 - Logic & Control - Part III   © Sri Lanka Institute of Information Technology
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   Basic Storage Elements
                                        If S = 1, R = 1 , Q = 0, Q = 0
                                         (Q and Q is same )
                                        Using this state

                                          If S = 0, R = 0 , Q = 1, Q = 0
                              0           If S = 0, R = 0 , Q = 0, Q = 1
                                          This is depend on the gate that we are
                                          going to start. So this is not reliable
                                          (Under level outputs. This is not used )


                                  This combination is not used



Computer Fundamentals (101)       Lecture 06 - Logic & Control - Part III   © Sri Lanka Institute of Information Technology
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   Characteristic of S-R Latch

                                            S                       R                  Q                   Q
                                            0                           0      Memory (As before)
                                            0                           1              0                    1
                                            1                           0              1                    0
                                            1                           1                  Not used




Computer Fundamentals (101)   Lecture 06 - Logic & Control - Part III       © Sri Lanka Institute of Information Technology
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   S-R Flip-Flops



           S=0 and R=0: Assume the flip flop is set (Q=0 and
            Q=1), then the output of the top NOR gate remains at
            Q=1 and the bottom NOR gate stays at Q=0.
           Similarly, when the flip flop is in a reset state (Q=1 and
            Q=0), it will remain there with this input combination.
           Therefore, with inputs S=0 and R=0, the flip flop
            remains in its state.


Computer Fundamentals (101)   Lecture 06 - Logic & Control - Part III   © Sri Lanka Institute of Information Technology
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   S-R Flip-Flops




            S=0 and R=1: Similar to the arguments above, the
             outputs become Q=0 and Q=1.
            We say that the flip flop is reset.




Computer Fundamentals (101)   Lecture 06 - Logic & Control - Part III   © Sri Lanka Institute of Information Technology
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   S-R Flip-Flops



            S=0 and R=0: Assume the flip flop is set (Q=0 and
             Q=1), then the output of the top NOR gate remains at
             Q=1 and the bottom NOR gate stays at Q'=0.
            Similarly, when the flipflop is in a reset state (Q=1 and
             Q'=0), it will remain there with this input combination.
            Therefore, with inputs S=0 and R=0, the flipflop remains
             in its state.
            S=1 and R=1: This input combination must be avoided.

Computer Fundamentals (101)   Lecture 06 - Logic & Control - Part III   © Sri Lanka Institute of Information Technology
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                Basic Storage Elements
                   (SR NAND latch)
      SR NAND latch can be built using 2 NAND
       Gates


                                                                            NAND Gate

                                                                            Truth table for NAND

                                                                            0          0              1
                                                                            0          1              1
                                                                            1          0              1
                                                                            1          1              0



Computer Fundamentals (101)   Lecture 06 - Logic & Control - Part III   © Sri Lanka Institute of Information Technology
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                   Clocked SR Flip Flop




Computer Fundamentals (101)   Lecture 06 - Logic & Control - Part III   © Sri Lanka Institute of Information Technology
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   SR Flip-flop




                                                                             Characteristic Table



Computer Fundamentals (101)   Lecture 06 - Logic & Control - Part III   © Sri Lanka Institute of Information Technology
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   D-Flip-Flop
      D-flip-flop is a slight modification of SR
       Flip-Flop.




Computer Fundamentals (101)   Lecture 06 - Logic & Control - Part III   © Sri Lanka Institute of Information Technology
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                               D Flip-flop




                                                                             Characteristic Table




Computer Fundamentals (101)   Lecture 06 - Logic & Control - Part III   © Sri Lanka Institute of Information Technology
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     JK Flip-flop




                                                                           Characteristic Table
      Input J and K behave like inputs S and R to set
       and reset respectively.
      When J = k = 1, a clock transition switches the
       output of the flip flop to their complement state.
Computer Fundamentals (101)   Lecture 06 - Logic & Control - Part III   © Sri Lanka Institute of Information Technology
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   Master Slave Flip Flop




Computer Fundamentals (101)   Lecture 06 - Logic & Control - Part III   © Sri Lanka Institute of Information Technology
   Flip-flops (Edge-triggered
                                                                                                                                       23




   Flip-flops)
          The storage elements employed in clocked sequential circuit
          A binary cell capable of storing one bit of information
          SR(Set/Reset) F/F           n D(Data) F/F
                 SET                                                            SET
            S           Q     S   R           Q(t+1)                      D             Q           D            Q(t+1)
                              0   0   Q(t)     no change                                            0        0   clear to 0
                              0   1    0       clear to 0                                           1        1     set to 1
                              1   0    1         set to 1                               Q
            R    CLR
                        Q                                                       CLR           “no change” condition: Q(t+1)=D
                              1   1    ?     Indeterminate
                                                                          1) Disable Clock 2) Feedback output into input
  n   JK(Jack/King) F/F                                           n      T(Toggle) F/F
                  SET         J   K         Q(t+1)
             J          Q                                                         SET
                              0   0   Q(t) no change                        T           Q            T             Q(t+1)
                              0   1    0     clear to 0                                              0      Q(t) no change
                              1   0    1       set to 1                                              1      Q'(t) Complement
             K          Q
                  CLR         1   1   Q(t)' Complement
                                                                                  CLR
                                                                                        Q
           JK F/F is a refinement of the SR F/F
                                                                            T=1(J=K=1), T=0(J=K=0) JK F/F
           The indeterminate condition of the SR type is
                                                                            Q(t+1)= Q(t)  T
             defined in complement
Computer Fundamentals (101)             Lecture 06 - Logic & Control - Part III             © Sri Lanka Institute of Information Technology
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                                                                                    Positive clock transition

 Edge-Triggered Flip Flops
           State Change : Clock Pulse
              Rising Edge(positive-edge transition)

              Falling Edge(negative-edge transition)
                                                           ts   th
           Setup time(20ns)
              Minimum time that D input must remain at constant value
               before the transition.
           Hold time(5ns)
              Minimum time that D input must not change after the positive
               transition.
           Propagation delay(max 50ns)
              time between the clock input and the response in Q

           Master-Slave F/F




Computer Fundamentals (101)   Lecture 06 - Logic & Control - Part III   © Sri Lanka Institute of Information Technology
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     Race
          Setup time > Propagation delay
                 7470 : J-K Edge triggered F/F
                 7471 : J-K Master/Slave F/F
     Excitation Table
          Required input combinations for a given change of state
          Present State Next State
                SR F/F                 JK F/F                          D F/F                     T F/F
         Q(t) Q(t+1)   S   R    Q(t) Q(t+1)   J      K           Q(t) Q(t+1)     D         Q(t) Q(t+1)        T
          0     0      0   X     0     0      0      X            0     0        0          0     0           0
          0     1      0   1     0     1      1      X            0     1        1          0     1           1
          1     0      1   0     1     0      X      1            1     0        0          1     0           1
          1     1      X   1     1     1      X      0            1     1        1          1     1           0



                        1 : Set to 1                                1 : Clear to 0
      Don’t Care                                                    0 : No change
                        0 : Complement

Computer Fundamentals (101)        Lecture 06 - Logic & Control - Part III     © Sri Lanka Institute of Information Technology

								
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