Introduction to DDR SDRAM by wLF1HSz

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									Introduction to
 DDR SDRAM
    Bill Gervasi
 Technology Analyst
wmgervasi@attbi.com




                      1
        Topics to Cover
•   The SDRAM Roadmap
•   Transitioning from SDR to DDR
•   DDR-I 400 Overview
•   Market overview




                                    2
     SDRAM Evolution
                                       5400MB/s
Mainstream
                                  4300MB/s
 Memories
                           3200MB/s
                   2700MB/s                  “DDR II”
             2100MB/s
                                        3200MB/s
        1600MB/s
  1100MB/s
                        “DDR I”
                                                 Simple,
        “SDR”
                                               incremental
                                                   steps
                                                        3
 Key to System Evolution
• Never over-design!
• Implement just enough new features to achieve
  incremental improvements
• Use low cost high volume infrastructure
   – Processes
   – Packages
   – Printed circuit boards




                                                  4
 From SDR to DDR
  Prefetch        Differential
     2              Clocks


 Write                Signaling
Latency               & Power

              Data
             Strobe
                                  5
                       Prefetch
• Today’s SDRAM architectures assume an inexpensive DRAM
  core timing

• DDR I (DDR200, DDR266, and DDR333) prefetches 2 data bits:
  increase performance without increasing core timing costs

• DDR II (DDR400, DDR533, DDR667) prefetches 4 bits
  internally, but keeps DDR double pumped I/O

• DDR-I 400 is a prefetch-2 architecture




                                                               6
            Prefetch Depth
CK
                      data
     READ                           SDR: Prefetch 1

 Core access                        DDR-I: Prefetch 2
    time
                                    DDR-II: Prefetch 4

 Costs $$$          Column cycle
                        time
                                   Essentially free
               Costs $$$
                                                7
Prefetch Impact on Cost
SDRAM     Pre-   Data   Cycle
Family   fetch   Rate   Time

          1      100    10 ns       High Yield =
SDR                                 Affordable
          1      133    7.5 ns
          2      200    10 ns
DDR-I     2      266    7.5 ns
          2      333     6 ns    Starts to get REAL
                                    EXPENSIVE!
          2      400    5 ns
DDR-II    4      400    10 ns
          4      533    7.5 ns
                                  Comparable to
                                  DDR266 in cost



                                               8
        DDR Data Timing
• Data valid on
  rising & falling
  edges… “Double
  Data Rate”
• Source
  Synchronous;
  Data Strobe
  “DQS” travels
  with data


                          9
 From SDR to DDR
  Prefetch        Differential
     2              Clocks


 Write                Signaling
Latency               & Power

              Data
             Strobe
                                  10
             DDR Clocks
• Differential clocks on adjacent traces
• Timing is relative to crosspoint
• Helps ensure 50% duty cycle




                                           11
Single Ended Clock
CK                                    VREF
 Normal
                      Clock   Clock
 balanced             high     low
 signal               time    time

CK                                    VREF
 Mismatched           Clock   Clock
 Rise & Fall          high     low
 signal      Error!
                      time    time



                                             12
     Differential Clock
CK
CK
               Clock      Clock
 Normal
 balanced      high        low
 signal        time       time
CK
CK
 Mismatched    Clock      Clock
 Rise & Fall   high        low
 signal        time       time
                Significantly reduced symmetry error
                                                 13
 From SDR to DDR
  Prefetch        Differential
     2              Clocks


 Write                Signaling
Latency               & Power

              Data
             Strobe
                                  14
               DDR Signaling
• SSTL_2 low voltage swing inputs
   – 2.5V I/O with 1.25V reference voltage
   – Low voltage swing with termination
   – Rail to rail if unterminated




                                             15
         Power = CV2f%#
Factors:
• Capacitance (C)        Keys to low
                        power design:
• Voltage (V)
• Frequency (f)
• Duty cycle (%)        Reduce C and V
                        Match f to demand
• Power states          Minimize duty cycle
  (# circuits in use)   Utilize power states




                                               16
Power: SDR  DDR-I DDR-II
  12                             DDR533
                                 @ 1.8V
  10
   8
   6                    DDR266
                        @ 2.5V
   4           PC-133
               @ 3.3V
   2
   0
       Throughput per Second per Unit Power




                                              17
 From SDR to DDR
  Prefetch        Differential
     2              Clocks


 Write                Signaling
Latency               & Power

              Data
             Strobe
                                  18
Emphasis on “Matched”
CONTROLLER                                DDR SDRAM

                    DQ/DQS

                             VREF




             VREF



                    DM

                              VREF


             VREF

                                Disable



         • DM/DQS loading identical to DQ
         • Route as independent 8bit buses
                                                      19
                                  64 = 8 x 8
• 64bit bus is 8 sync’ed 8bit buses
• Allows external “copper” flexibility
• 8 buses resync upon entry to FIFO
                      x16 DDR               x16 DDR   x16 DDR     x16 DDR
  Copper
                      SDRAM                 SDRAM     SDRAM       SDRAM
    from
 controller                 8 DQ    8 DQ                                     8 DQ
to SDRAMs                   1 DM    1 DM                                     1 DM
                            1 DQS   1 DQS                                    1 DQS
          Inside    8bit Buffer                                       8bit Buffer
         Controller
 Sync to
Controller                    64bit Memory Controller Internal FIFO
  clock




                                                                                20
 From SDR to DDR
  Prefetch        Differential
     2              Clocks


 Write                Signaling
Latency               & Power

              Data
             Strobe
                                  21
              Write Latency
• SDR had to keep inputs powered all the time
• Adding Write Latency to DDR allowed inputs to be
  powered off between commands
• Flexible timing differences on data and address paths




                                                      22
DDR-I vs DDR-II @ 400
        3200MB/s
                        “DDR II”

 2700MB/s




                   3200MB/s
   “DDR I”

                              23
           DDR-I 400 Summary
• DDR-I is hard to design to 400 MHz data rate
   – Lower yields
       • No JEDEC standard
       • Prefetch-2, 2.5V signals, TSOP packages, write latency 1
   – DDR-II makes it a lot easier
       •   JEDEC standards & focus
       •   Prefetch-4, 1.8V signals, differential strobe
       •   On-die termination, BGA packages, write latency > 1
       •   Same plane referencing
• Few suppliers supporting DDR-I 400 market



                                                                    24
     DDR-I 400 Conclusion
• The JEDEC roadmap represents the industry
  focus for mainstream products
  – DDR-I tops out at 333 MHz data rate
  – DDR-II starts at 400 MHz data rate
• This DOES NOT mean that DDR-I at 400
  MHz data rate will not ship in volume
• It DOES mean that there will be price
  premiums for this speed bin


                                              25
           Market Outlook
• DDR-I
  – DDR333 is the mainstream product for 2003
  – DDR-I 400 will be the premium market
• DDR-II
  – DDR-II designs under way now
  – DDR-II 400 & 533 will sample in 2003
  – DDR-II ramp begins in 2004


                                                26
                  Summary
• DDR has many improvements over SDR
  – Prefetch, differential clock, low voltage, data
    strobe, write latency
• DDR-I 400 likely to stay a profitable niche
• DDR-II volume products for 400 & 533 ramp
  in 2004



                                                      27
Thank You



            28

								
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