# PLL Concepts

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```					PLL Concepts

   The operation of a phase locked loop, PLL, is based around the idea of comparing the phase of
two signals. The phase difference between the two signals is then used to control the
frequency of a loop.

   To look at the concept of phase difference, take the example of two signals. Although the two
signals have the same frequency, when the peaks and troughs do not occur in the same place
there is said to be a phase difference between the two signals

   This phase difference is measured as angle between them.

   When two signals have different frequencies, the phase difference between them is always
varying. The reason for this is that the time for each cycle is different and accordingly they are
moving around the circle at different rates.

   It can be inferred from this that the meaning of two signals having exactly the same frequency is
that the phase difference between them is constant. If the phase difference is fixed it means
that one is lagging behind or leading the other signal by the same amount, i.e. they are on the
same frequency.

What is a PLL ?

   Basically , A Phase-Locked Loop (PLL) device is a closed-loop electronic circuit that controls an
oscillator so that it provides an output signal that maintains a constant phase angle with respect
to a reference input signal, which can range from a fraction of a Hz to many GHz.

   A PLL, consists of three basic elements:

   (1) Phase comparator or detector: This circuit (which can also be implemented using X-OR
gate) compares the phase of the input voltage with that of the VCO output voltage and
produces a low frequency voltage according to the phase difference between the two signals.

   (2) Loop filter: It removes any high frequency component from the output of the phase
comparator and provides a clean dc voltage which is applied to the control (tuning) input of
the VCO whose output frequency is proportional to the dc value. This promotes loop stability.

   3) Voltage controlled oscillator (VCO): This circuit block generates the output radio frequency
signal. Its frequency can be controlled and swung over the operational frequency band for the
loop.

   If the frequency of the input signal shifts slightly, the phase difference between the input signal
and the VCO output voltage will begin to increase with time.

   The VCO frequency is then adjusted by the control voltage continuously until it is equal to
the input frequency.
   PLL BLOCK DIAGRAM

PLL …. Operation

   The phase of the signals from the VCO and the incoming reference signal are compared and the
resulting difference is an error voltage.

   This error signal generated is actually noisy because it consists of an error term and a noise
term.

   The error signal then passes through a low pass filter which governs the properties of the loop
and removes any high frequency elements on the signal. After this process, the useful error
signal is applied to the control terminal of the VCO as its tuning voltage.

   The sense of the useful error voltage is that it tries to reduce the phase difference and hence
the frequency between the two signals while suppressing the effect of the noise as much as
possible

   Initially the loop will be out of lock, and the error voltage will pull the frequency of the VCO
towards that of the reference, until it cannot reduce the error any further and the loop is
locked.

   When the PLL is in lock , a steady state error voltage is produced. The fact that a steady error
voltage is present means that the phase difference between the reference signal and the VCO
is not changing. As the phase between these two signals is not changing means that the two
signals are exactly on the same frequency.

   Initially the loop will be out of lock, and the error voltage will pull the frequency of the VCO
towards that of the reference, until it cannot reduce the error any further and the loop is
locked.
   When the PLL is in lock , a steady state error voltage is produced. The fact that a steady error
voltage is present means that the phase difference between the reference signal and the VCO
is not changing. As the phase between these two signals is not changing means that the two
signals are exactly on the same frequency.

What is PLL capable to do?

It has the capability to do one or more of the following:

   1) compare signal frequencies;

   2) synthesize or integrate an output signal that has a frequency that's equal to that of a
reference signal;

3) keep another signal equal in frequency with the reference signal.

Session 15: Modes of PLL Operation

Operation involves three modes namely:

   Free Running mode

   Capture mode

   Phase-lock mode

Free Running mode

During this mode,

   There is no application of Input signal

   VCO runs at a fixed resonant or free running frequency (fo)that corresponds to the zero input
voltage applied.

Capture Mode

   When an input signal is applied, the VCO frequency begins to change continuously to match the
input signal frequency. This sets the PLL into Capture mode

Capture range is the band of frequencies around the resonant frequency(fo) where the PLL can
establish or acquire lock with an input or external signal from an unlocked condition. This range is also
known as the Acquisition range and is related to the low-pass filter bandwidth

Phase- Lock Mode
   As the VCO frequency begins to change continuously to match the input signal frequency, the
input frequency becomes equal to the output frequency. This sets the PLL in the Phase- lock
mode

   The feedback loop will maintain the lock when the frequency of the input signal changes.

   Lock range is the range of input frequencies in the vicinity of the resonant frequency, over
which the PLL can maintain lock with an input signal.

   It is also known as the tracking or holding range. Lock range increases as the overall gain of the
PLL is increased.

   In the lock state, the VCO output frequency is lock onto or equal to the frequency of the
external input signal.

How the PLL Gains Lock

   The input clock frequency must stay within the minimum and maximum lock frequency,
generally the mid-point of the VCO operating range to match the Phase Comparator input
frequency.

   A high bandwidth allows the loop to respond quickly to noise and compensates for it to gain
lock. A PLL can typically lock to and track an input signal over a bandwidth of +60% or -60% of
the center frequency.

How the PLL loses LOCK

   Excessive jitter on the input clock can cause the PLL to lose lock

   Power supply noise on VCO supply could cause the VCO output frequency to fluctuate and
cause jitter.

   A low bandwidth causes the loop to respond slower to the noise being injected by the VCO.

Applications………….

   Frequency synchronisation and signal conditioning

a poor oscillator can be locked to good reference signal - eg colour TV

   Remove out-of-range interference, ie phase jitter

   Synchronisation for control of :

motor speed - required for many applications, e.g. CD player.
   Frequency synthesis

multiply reference frequency by N, by dividing output in feedback loop

   Frequency translation

by adjusting response to out of phase signal at input, can offset by small diff in freq.

   Tone or carrier detection . Simply detect if a given frequency is present with magnitude above
threshold . Useful eg in stereo decoders, modem

   FM demodulation

PLL tracks variation in frequency also used in Frequency-shift keying - where mark/space ratio
changes,

   AM detection

If input is sinusoidal, then PLL can demodulate signal from carrier.

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