embedded systems and micro controller by ashok453



               An embedded system is a special-purpose system in which the computer is
completely encapsulated by or dedicated to the device or system it controls. Unlike a general-
purpose computer, such as a personal computer, an embedded system performs one or a few pre-
defined tasks, usually with very specific requirements. Since the system is dedicated to specific
tasks, design engineers can optimize it, reducing the size and cost of the product. Embedded
systems are often mass-produced, benefiting from economies of scale.

Personal digital assistants (PDAs) or handheld computers are generally considered embedded
devices because of the nature of their hardware design, even though they are more expandable in
software terms. This line of definition continues to blur as devices expand.

Physically, embedded systems range from portable devices such as digital watches and MP3
players, to large stationary installations like traffic lights, factory controllers, or the systems
controlling nuclear power plants.

In terms of complexity embedded systems can range from very simple with a single
microcontroller chip, to very complex with multiple units, peripherals and networks mounted
inside a large chassis or enclosure.

Examples of embedded systems

      Automatic teller machines (ATMs)
      Avionics, such as inertial guidance systems, flight control hardware/software and other
       integrated systems in aircraft and missiles
      Cellular telephones and telephone switches
      engine controllers and antilock brake controllers for automobiles
      Home automation products, such as thermostats, air conditioners, sprinklers, and security
       monitoring systems
      Handheld calculators
      Handheld computers
      Household appliances, including microwave ovens, washing machines, television sets,
        DVD players and recorders
       Medical equipment
       Personal digital assistant
       Videogame consoles
       Computer peripherals such as routers and printers
       Industrial controllers for remote machine operation.


             In the earliest years of computers in the 1940s, computers were sometimes dedicated to
a single task, but were too large to be considered "embedded". Over time however, the concept
of programmable controllers developed from a mix of computer technology, solid state devices,
and traditional electromechanical sequences.

             The first recognizably modern embedded system was the Apollo Guidance Computer,
developed by Charles Stark Draper at the MIT Instrumentation Laboratory. At the project's
inception, the Apollo guidance computer was considered the riskiest item in the Apollo project.
The use of the then new monolithic integrated circuits, to reduce the size and weight, increased
this risk.

             The first mass-produced embedded system was the Automatics D-17 guidance
computer for the Minuteman (missile), released in 1961. It was built from transistor logic and
had a hard disk for main memory. When the Minuteman II went into production in 1966, the D-
17 was replaced with a new computer that was the first high-volume use of integrated circuits.
This program alone reduced prices on quad nand gate ICs from $1000/each to $3/each,
permitting their use in commercial products.

              Since these early applications in the 1960s, embedded systems have come down in
price. There has also been an enormous rise in processing power and functionality. For example
the first microprocessor was the Intel 4004, which found its way into calculators and other small
systems, but required external memory and support chips.
             In 1978 National Engineering Manufacturers Association released the standard for a
programmable microcontroller. The definition was an almost any computer-based controller.
They included single board computers, numerical controllers, and sequential controllers in order
to perform event-based instructions.By the mid-1980s, many of the previously external system
components had been integrated into the same chip as the processor, resulting in integrated
circuits called microcontrollers, and widespread use of embedded systems became feasible.

             As the cost of a microcontroller fell below $1, it became feasible to replace
expensive knob-based analog components such as potentiometers and variable capacitors with
digital electronics controlled by a small microcontroller with up/down buttons or knobs. By the
end of the 80s, embedded systems were the norm rather than the exception for almost all
electronics devices, a trend which has continued since.


        Embedded systems are designed to do some specific task, rather than be a general-
purpose computer for multiple tasks. Some also have real-time performance constraints that must
be met, for reason such as safety and usability; others may have low or no performance
requirements, allowing the system hardware to be simplified to reduce costs.

        An embedded system is not always a separate block - very often it is physically built-in
to the device it is controllingThe software written for embedded systems is often called
firmware, and is stored in read-only memory or Flash memory chips rather than a disk drive. It
often runs with limited computer hardware resources: small or no keyboard, screen, and little

User interfaces

           Embedded systems range from no user interface at all - dedicated only to one task - to
full user interfaces similar to desktop operating systems in devices such as PDAs.

Simple systems
           Simple embedded devices use buttons, LEDs, and small character- or digit-only
displays, often with a simple menu system.

In more complex systems

      A full graphical screen, with touch sensing or screen-edge buttons provides flexibility
while minimizing space used: the meaning of the buttons can change with the screen, and
selection involves the natural behavior of pointing at what's desired.Handheld systems often have
a screen with a "joystick button" for a pointing device.

     The rise of the World Wide Web has given embedded designers another quite different
option: providing a web page interface over a network connection. This avoids the cost of a
sophisticated display, yet provides complex input and display capabilities when needed, on
another computer. This is successful for remote, permanently installed equipment. In particular,
routers take advantage of this ability.

3.3CPU platform

     Embedded processors can be broken into two distinct categories: microprocessors (μP) and
micro controllers (μC). Micro controllers have built-in peripherals on the chip, reducing size of
the system.There are many different CPU architectures used in embedded designs such as ARM,
MIPS, Coldfire/68k, PowerPC, x86, PIC, 8051, Atmel AVR, Renesas H8, SH, V850, FR-V,
M32R, Z80, Z8, etc. This in contrast to the desktop computer market, which is currently limited
to just a few competing architectures.

         PC/104 and PC/104+ are a typical base for small, low-volume embedded and rugged
system design. These often use DOS, Linux, NetBSD, or an embedded real-time operating
system such as QNX or VxWorks.A common configuration for very-high-volume embedded
systems is the system on a chip (SoC), an application-specific integrated circuit (ASIC), for
which the CPU core was purchased and added as part of the chip design. A related scheme is to
use a field-programmable gate array (FPGA), and program it with all the logic, including the


Embedded Systems talk with the outside world via peripherals, such as:

       Serial Communication Interfaces (SCI): RS-232, RS-422, RS-485 etc
       Synchronous Serial Communication Interface: I2C, JTAG, SPI, SSC and ESSI
       Universal Serial Bus (USB)
       Networks: Controller Area Network, LonWorks, etc
       Timers: PLL(s), Capture/Compare and Time Processing Units
       Discrete IO: aka General Purpose Input Output (GPIO)


          As for other software, embedded system designers use compilers, assemblers, and
debuggers to develop embedded system software. However, they may also use some more
specific tools:

       An in-circuit emulator (ICE) is a hardware device that replaces or plugs into the
        microprocessor, and provides facilities to quickly load and debug experimental code in
        the system.
       Utilities to add a checksum or CRC to a program, so the embedded system can check if
        the program is valid.
       For systems using digital signal processing, developers may use a math workbench such
        as MathCad or Mathematica to simulate the mathematics.
      Custom compilers and linkers may be used to improve optimization for the particular
      An embedded system may have its own special language or design tool, or add
       enhancements to an existing language.

Software tools can come from several sources:

      Software companies that specialize in the embedded market
      Ported from the GNU software development tools
      Sometimes, development tools for a personal computer can be used if the embedded
       processor is a close relative to a common PC processor


              Embedded Debugging may be performed at different levels, depending on the
facilities available, ranging from assembly- or source-level debugging with an in-circuit emulator
or in-circuit debugger, to output from serial debug ports or JTAG/Nexus interfaces, to an
emulated environment running on a personal computer.

              As the complexity of embedded systems grows, higher level tools and operating
systems are migrating into machinery where it makes sense. For example, cell phones, personal
digital assistants and other consumer computers often need significant software that is purchased
or provided by a person other than the manufacturer of the electronics. In these systems, an open
programming environment such as Linux, NetBSD, OSGi or Embedded Java is required so that
the third-party software provider can sell to a large market.


            Embedded systems often reside in machines that are expected to run continuously for
years without errors, and in some cases recover by themselves if an error occurs. Therefore the
software is usually developed and tested more carefully than that for personal computers, and
unreliable mechanical moving parts such as disk drives, switches or buttons are avoided.
Recovery from errors may be achieved with techniques such as a watchdog timer that resets the
computer unless the software periodically notifies the watchdog.

Specific reliability issues may include:

   1. The system cannot safely be shut down for repair, or it is too inaccessible to repair.
       Solutions may involve subsystems with redundant spares that can be switched over to, or
       software "limp modes" that provide partial function. Examples include space systems,
       undersea cables, navigational beacons, bore-hole systems, and automobiles.
   2. The system must be kept running for safety reasons. "Limp modes" are less tolerable.
       Often backups are selected by an operator. Examples include aircraft navigation, reactor
       control systems, safety-critical chemical factory controls, train signals, engines on single-
       engine aircraft.
   3. The system will lose large amounts of money when shut down: Telephone switches,
       factory controls, bridge and elevator controls, funds transfer and market making,
       automated sales and service.

High vs Low Volume

         For high volume systems such as portable music players or mobile phones, minimizing
cost is usually the primary design consideration. Engineers typically select hardware that is just
“good enough” to implement the necessary functions.For low-volume or prototype embedded
systems, general purpose computers may be adapted by limiting the programs or by replacing the
operating system with a real-time operating system.

Embedded software architectures

There are several different types of software architecture in common use.

Simple control loop

                   In this design, the software simply has a loop. The loop calls subroutines,
each of which manages a part of the hardware or software.
Interrupt controlled system

         Some embedded systems are predominantly interrupt controlled. This means that tasks
performed by the system are triggered by different kinds of events. An interrupt could be
generated for example by a timer in a predefined frequency, or by a serial port controller
receiving a byte.These kinds of systems are used if event handlers need low latency and the
event handlers are short and simple.

         Usually these kinds of systems run a simple task in a main loop also, but this task is not
very sensitive to unexpected delays. The tasks performed in the interrupt handlers should be kept
short to keep the interrupt latency to a minimum.Some times longer tasks are added to a queue
structure in the interrupt handler to be processed in the main loop later. This method brings the
system close to a multitasking kernel with discrete processes.

Cooperative multitasking

             A no preemptive multitasking system is very similar to the simple control loop
scheme, except that the loop is hidden in an API. The programmer defines a series of tasks, and
each task gets its own environment to "run" in. Then, when a task is idle, it calls an idle routine
(usually called "pause", "wait", "yield", etc.).The advantages and disadvantages are very similar
to the control loop, except that adding new software is easier, by simply writing a new task, or
adding to the queue-interpreter.


             The 89c51RD2xx is a low-power, high-performance CMOS 8-bit microcomputer
with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is
manufactured using Philips high-density nonvolatile memory technology and is compatible with
inustry-standard MCS-51 instruction set and pin out. The on-chip Flash allows the program
memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer.
By combining a versatile 8-bit CPU with Flash on a monolithic chip, the P89C51RD2xx is a
powerful microcomputer which provides a highly-flexible and cost-effective solution to many
embedded control applications.


      Compatible with MCS-51 Products
      4K Bytes of In-System Reprogrammable Flash Memory – Endurance: 1000 Write/Erase
      Fully Static Operation: 0
      Hz to 24MHz
      Three-level Program Memory Lock
      128 x 8- bit Internal RAM
      32 Programmable I/O Lines
     VCC power supply
     GND Grou
      Port 0 Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin
can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-
impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus
during accesses to external program and data memory. In this mode, P0 has internal pull-ups.
Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-ing
program verification. External pull-ups are required during program verification.
         Port 1    Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1
output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are
pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are
externally being pulled low will source current (IIL) because of the internal pull-ups. Port 1 also
receives the low-order address bytes during Flash programming and verification.
         Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2
output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are
pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are
externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2
emits the high-order address byte during fetches from external program memory and dur-ing
accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this
application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special
Function Register. Port 2 also receives the high-order address bits and some control signals
during Flash program-ming and verification.
        Port3 Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output
buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high
by the inter- Port Pin Alternate Functions P1.5 MOSI (used for In-System Programming) P1.6
MISO (used for In-System Programming) P1.7 SCK (used for In-System Programming)5
2487D–MICRO–6/08 AT89S51 nal pull-ups and can be used as inputs. As inputs, Port 3 pins
that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3
receives some control signals for Flash programming and verification.
       RST Reset input. A high on this pin for two machine cycles while the oscillator is
running resets the device. This pin drives High for 98 oscillator periods after the Watchdog times
out. The DIS-RTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the
default state of bit DISRTO, the RESET HIGH out feature is enabled.
          ALE/PROG          Address Latch Enable (ALE) is an output pulse for latching the low
byte of the address during accesses to external memory. This pin is also the program pulse input
(PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency and may be used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped dur-ing each access to external data memory. If desired,
ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is
active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high.
          PSEN Program Store Enable (PSEN) is the read strobe to external program memory.
When the AT89S51 is executing code from external program memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each access to exter-
nal data memory.
           EA/VPP        External Access Enable. EA must be strapped to GND in order to enable
the device to fetch code from external program memory locations starting at 0000H up to
FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.
Port Pin Alternate Functions P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2
INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3.4 T0 (timer 0 external input) P3.5
T1 (timer 1 external input) P3.6 WR (external data memory write strobe) P3.7 RD (external data
memory read strobe)6 2487D–MICRO–6/08 AT89S51 EA should be strapped to VCC for
internal program executions. This pin also receives the 12-volt programming enable voltage
(VPP) during Flash programming.
       XTAL1         Input to the inverting oscillator amplifier and input to the internal clock
operating circuit.
       XTAL2 Output from the inverting oscillator amplifi
                     Figure.1 Block Diagram of the AT89C core

                                                    TIMER 1
                                                    ON-CHIP      COUNTER
                                                    TIMER 0
                   ON-CHIP         ON-CHIPRAM                    INPUTS
INTERRUPT                                             RAM
  CONTROL           FLASH


                                    4 I/O PORTS
   OSC       BUS


                                   PO P2 P1 P3    TXD

                             Fig.1 Oscillator Connection.

       The P89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of
RAM, 32 I/O lines, two 16-bit timer/counters, five vector two-level interrupt architecture, a full
duplex serial port, on-chip oscillator and clock circuitry. In addition, the P89C51 is designed
with static logic for operation down to zero frequency and supports two software selectable
power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,
serial port acontents but freezes the oscillator disabling all other chip functions until the next


          OSCILLATOR                      XTAL1



                                   DATA MEMORY
Fig.2 External Clock






     EA = 0                EA = 1
                                      0               0000
     External              External   0
                                      0                       RD   WR

Fig.3 Memory Structure of the 8051.
4.4Memory Organization

Program Memory

               Figure 4 shows a map of the lower part of the program memory. After reset, the
CPU begins execution from location 0000H. As shown in fig.4, each interrupt is assigned a fixed
location in program memory. The interrupt causes the CPU to jump to that location, where it
executes the service routine. External Interrupt 0, for example, is assigned to location 0003H. If
External Interrupt 0 is used, its service routine must begin at location 0003H. If the interrupt is
not used, its service location is available as general purpose.



                                                                  8 bytes

               RESET                                001BH

Fig. 4 Program Memory.


Program memory addresses are always 16 bits wide, even though the actual amount o program
memory used may be less than 64Kbytes. External program execution sacrifices two of the 8-bit
ports, P0 and P2, to the function of addressing the program memory.

Data Memory

       The right half of Figure 3 shows the internal and external data memory spaces available
on Philips Flash microcontrollers. Fig.6 shows a hardware configuration for accessing up to 2K
bytes of external RAM. In this case, the CPU executes from internal flash. Port0 serves as a
multiplexed address/data bus to the RAM, and 3 lines of Port 2 are used to page the RAM. The
CPU generates RD and WR signals as needed during external RAM accesses. You can assign up
to 64K bytes of external data memory. External data memory addresses can be either 1 or 2bytes
wide. One-byte addresses are often used in conjunction with one or more other I/O lines to page
the RAM, as shown in Fig.6. Two-byte addresses can also be used, in which case the high
address byte is emitted at Port2.

             FFH     ACCESSIBLE BY    ACCESSIBLE BY       FFH
         Upper         INDIRECT          DIRECT
         128          ADDRESSING       ADDRESSING
                         ONLY.            ONLY
                     ACCESSIBLE BY
           7FH                                                     Ports
         Lower       INDIRECT
                     ADDRESSING                                    Status and
         128                                   Special
                     AND DIRECT                                     control bits
                                               register   80H      Timers
             00      ADDRESSING
                                               function            Registers
                                                                   Stack pointer
                                                                   Accumulator
                      Fig.5 Internal Data Memory.                  (etc)
       Internal data memory addresses are always 1 byte wide, which implies an address space
of only 256bytes. However, the addressing modes for internal RAM can infact accommodate 384
bytes. Direct addresses higher than 7FH access one memory space and indirect addresses higher
than 7FH access a different memory space. Thus, Figure.7 shows the Upper 128 and SFR space
occupying the same block of addresses, 80H through FFH, although they are physically separate
entities. Figure.8 shows how the lower 128 bytes of RAM are mapped. The lowest 32 bytes are
grouped into 4 banks of 8 registers. Program instructions call out these registers as R0 through
R7. Two bits in the Program Status Word (PSW) select which register bank is in use. This
architecture allows more efficient use of code space, since register instructions are shorter than
instructions that use direct addressing.

Fig.6 The lower 128 bytes of Internal RAM
              The next 16 bytes above the register banks form a block of bit-addressable memory
space. The microcontroller instruction set includes a wide selection of single-bit instructions, and
these instructions can directly address the 128 bits in this area. These bit addresses are 00H
through 7FH. All of the bytes in the Lower 128 can be accessed by either direct or indirect

Special Function Register Map

8 Bytes

F8                                                                                    FF
F0 B                                                                                  F7
E8                                                                                    EF
E0 ACC                                                                                E7
D8                                                                                    DF
D0 PSW(1)                                                                             D7
C8 T2C0N(1 T2MOD( RCAP2L(2) RCAP2H( TL2(2) TH2(                                       CF
C0 )(2)      2)             2)             2)                                         C7
B8 IP(1)                                                                              BF
B0 P3                                                                                 B7
A8 IE(1)                                                                              AF
A0 P2                                                                                 A7
98 SCON(1) SBUF                                                                       9F
90 PI                                                                                 97
88 TCON(1) TMOD(1) TLO      TLI     THO TH1                                           BF
80 PO        SP    DPL      DPH                 PCON(1)                               87
Bit Addressable

Notes: 1. SFRs converting mode or control bits

          2. AT89C52only

Power-on Reset
                 The reset input is the RST pin, which is the input to a Schmitt Trigger. A reset is
accomplished by holding the RST pin high for at least two machine cycles (24 oscillator
periods), while the oscillator is running. The CPU responds by generating an internal reset.

                 The external reset signal is asynchronous to the internal clock. The RST pin is
sampled during State 5 Phase 2 of every machine cycle. The port pins will maintain their current
activities for 19 oscillator periods after a logic 1 has been sampled at the RST pin; that is, for 19
to 31 oscillator periods after the external reset signal has been applied to the RST pin. The
internal reset algorithm writes 0s to all the SFRs except the port latches, the Stack Pointer and
SBUF. The port latches are initialized to FFH, the Stack Pointer to 07H, and SBUF is
indeterminate. The internal RAM is not affected by reset. On power up the RAM content is


                 The P89C51 provides 5 interrupt sources. The External Interrupts INT0 and INT1
can each be either level-activated or transition-activated, depending on bits IT0 and IT1 in
Register TCON. The flags that actually generate these interrupts are bits IE0 and IE1 in TCON.
When an external interrupt is generated, the flag that generated it is cleared by the hardware
when the service routine is vectored to only if the interrupt was transition-activated. If the
interrupt was level-activated, then the external requesting source is what controls the request
flag, rather than the on-chip hardware.

                 The Timer0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set
by a rollover in their respective Timer/Counter registers (except see Timer0 in Mode3). When a
timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when
the service routine is vectored to.

                            The Serial Port Interrupt is generated by the logical OR of RI and TI.
Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the
service routine will normally have to determine whether it was RI or TI that generated the
interrupt, and the bit will have to be cleared in software.
          All of the bits that generate interrupts can be set or cleared by software, with the same
result as thought it had been set or cleared by hardware. This is, interrupts can be generated or
pending interrupts can be canceled in software.

          Each of these interrupt sources can be individually enabled or disabled by setting or
clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which
disables all interrupts at once.

          The interrupt flags are sampled a S5P2 of every machine cycle. The samples are polled
during the following machine cycle. If one of the flags was in a set condition at S5P2 of the
preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to
the appropriate service routine, provided this hardware-generated LCALL is not blocked by any
of the following conditions:

    1.    An interrupt of equal or higher priority level is already in progress.
    2.    The current (polling) cycle is not the final cycle in the execution of the instruction in
    3.    The instruction in progress is RET1 or any write to the IE or IP registers.
          Any of these three conditions will block the generation of the LCALL to the interrupt
service routine. Condition 2 ensures that instruction in progress will be completed before
vectoring to any service routine. Condition 3 ensures that if the instruction in progress is RET1
or any access to IE or IP, then at least one more instruction will be executed before any interrupt
is vectored to.

          The poling cycle is repeated with each machine cycle, and the values polled are the
values that were present at S5P2 of the previous machine cycle. Note that if any interrupt flag is
active but not being responded for one of the above conditions, if the flag is not still active when
the blocking condition is removed, the denied interrupt will not be serviced. In other words, the
fact that the interrupt flag was once active but not serviced is not remembered. Every polling
cycle is new.
          The processor acknowledges an interrupt request by executing hardware generated
LCALL to the appropriate servicing routine. In some cases it also clears the flag that generated
the interrupt, and in other cases it doesn’t. It never clears the Serial Port flag. This has to be done
in the user’s software. It clears an external interrupt flag (IE0 or IE1) only if it was transition-
activated. The hardware generated LCALL pushes the contents of the Program Counter onto the
Stack (but it does not save the PSW) and reloads the PC with an address that depends on the
source of the interrupt being vectored to. Execution proceeds from that location until the RET1
instruction is encountered. The RET1 instruction informs the processor that this interrupt routine
is no longer in progress, then pops the top two bytes from the stack and reloads the Program
Counter. Exception of the interrupted program continues fro where it left off.

          Note that a simple RET instruction would also have returned execution to the
interrupted program, but it would have left the interrupt control system thinking an interrupt was
still in progress, making future interrupts impossible.

External Interrupts

                The external sources can be programmed to be level-activated or transition-
activated by setting or clearing bit IT1 or IT0 in Register TCON. If ITx=0, external interrupt x is
triggered by a detected low at the INTX pin. If ITx=1, external pin x is edge triggered. In this
mode if successive samples of the INTX pin show a high in one cycle and a low in the next
cycle, interrupt request flag IEx in TCON is set. Flag bit IEx then request the interrupt.

                Since the external interrupt pins are sampled once each machine cycle, an input
high or low should hold for at least 12 oscillator periods to ensure sampling. If the external
interrupt is transition-activated, the external source has to hold the request pin high for at least
once cycle, and then hold it low for at least one cycle. This is done to ensure that transition is
seen so that interrupt request flag IEx will be set. The CPU will automatically clear IEx when the
service routine is called.
                 If the external interrupt is level-activated, the external source has to hold the request
active until the requested interrupt is actually generated. Set the EA (enable all) bit in the IE
register to 1.

      1. Set the corresponding individual interrupt enable bit in the IE register to 1.
      2. Begin the interrupt service routine at the corresponding vector.
                 In addition, for external interrupts, pins INT0 and INT1(P3.2 and P3.3) must be set
to 1, and depending on whether the interrupt is to be level or transition activated, bits IT0 or IT1
in the TCON register may need to be set to 1.

ITx=0                             level activated

ITx=1                             transition activated Priority within level is only to resolve
simultaneous requests of the same priority level. Form high to low, interrupt sources are listed

IE0                       highest priority



TF1R1 or T1 lowest priority


Timer Set-Up

                  The tables below give some values for TMOD which can be used to set up Timer
0 and Timer 1 in different modes. It is assumed that only one timer is being used at a time. If it is
desired to run Timers 0 and 1 simultaneously, in any mode the value in the TMOD for timer 0
must be ORed with value shown for Timer 1. For example, if it is desired to run Timer 0 in mode
1 GATE (external control), and Timer 1 in mode 2 COUNTER, then value that must be loaded
into TMOD is 69H (09H from the table for Timer0, ORed with 60H from the table for Timer 1).

                  Moreover, it is assumed that the user, at this point, is not ready to turn the timers
on and will do that at a different point in the program by setting bit TRx (in TCON) to

As a Timer:

Mode          Function        TMOD (internal control)    TMOD (external

0             13-bit Timer     00H                08H

1             16-bit Timer     01H                 09H

2             8-bit Auto-Reload 02H               0AH

3          Two 8-bit Timers    03H                0BH


As a Timer:

Mode          Function        TMOD (internal control)    TMOD (external

0             13-bit Timer     00H                80H

1             16-bit Timer     10H                 90H
2               8-bit Auto-Reload 20H                               A0H

3            Does not run             30H                           B0H

As a Counter

Mode                Function          TMOD (internal control)                  TMOD (external

0               13-bit Counter        40H                           C0H

1               16-bit Counter         50H                          D0H

2               8-bit Auto-Reload 60H                               A0H

3            Not available             ---                          ---

Serial Port Set-Up

            The serial port is full duplex, meaning it can transmit and receive simultaneously. It
is also receive-buffered, meaning it can commence reception of a second byte before a
previously received byte has been read form the register. (However, if the first byte still hasn’t
been read by the time reception of the second byte is complete, one of the bytes will be lost.) The
serial port receive and transmit registers are both accessed at Special Function Register SBUF.
Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate
receive register.

The serial port can operate in 4 modes:

           Mode 0: Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits
are transmitted/received (LSB first). The baud rate is fixed at 1/12th oscillator frequency.
          Mode 1: 10 bits are transmitted (through TxD) or received (through RxD): a start bit
(0), 8 data bits (LSB first), and a stop bit (1). On receive; the stop bit goes into RB8 in Special
Function Register SCON. The baud rate is variable.

           Mode 2: 11 bits are transmitted (trough TxD) or received (through RxD): start bit (0),
8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit
(TB is SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW)
could be moved into TB8. On receive; the 9th data bit goes into RB8 in Special Function Register
SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64th
oscillator frequency.

         Mode 3: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0),
8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the same
as Mode2 in all aspects except baud rate. The baud rate in Mode 3 is variable.

MODESCON SM2 Variation

0      10H Single Processor

1                  50H               Environment

2                  90H               (SM2 = 0)


Serial Port in Mode 0:

                   Mode 0 has a fixed baud rate, which is 1/12th oscillator frequency. To run the
serial port in this mode none of the Timer/Counters need to be set up. Only the SCON register
needs to be defined.
Baud Rate = Oscillator Frequency /12

Serial Port in Mode 1:

Mode1 has a variable baud rate. The baud rate is generated by Timer 1.

For this purpose, Timer 1 is used in mode2 (Auto-Reload).

Baud Rate = (K x Osc.Freq) / (32 x 12 x [256 – (TH1)])

               Circuit of 8051

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