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Lecture 19

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					CAD for VLSI Design - II


              Lecture - 19
  V. Kamakoti and Shankar Balachandran
                Overview
• Logical Effort and Gain Based Synthesis
  – Addressing timing and power issues at
    synthesis stage
        Traditional ASIC Design Flow
                  RTL          Constraints • The majority of designs are synthesized
                                                 using wireload models
                                                  • Traditional synthesis engines require an
                                                    estimate of the output load capacitance
                        Synthesis
                                                    in order to determine the cell delay
   Library
                                                  • A lot of runtime is consumed during
wireload models
                              Meets timing          synthesis to perform cell sizing based
   defined in
     library                  after synthesis       on the inaccurate wire load estimate

                                                • The design fails timing after physical
                        Place and
                          Route
                                                  design
                                                   • The wireload models were too
       Fails timing after                            optimistic during synthesis
       physical design                             • A vast majority of gates need to be re-
                                                     sized to drive the actual load after
                                                     placement
                        Final Design
                                                   • Objective is to arrive at QUICK TIMING
                                                     CLOSURE
 Cell Delay vs Load vs Cell Size
    Delay -vs- Load                                         Size -vs- Load
                         Cell delay is a function
                         of the total output load
                           and cell size (drive)
Delay                                                Size



                  Load                                                   Load
                                    Delay
    Cell size is fixed                                  Cell delay is fixed



                                              Size



                            Load
Delay vs Load - Traditional Flow
      Delay -vs- Load                      Delay




  Delay
                                                          Load
                                         Cell size
                                         is fixed
                   Load

• A traditional synthesis tools operate in the "delay vs load" plane
• Cell sizes are fixed during synthesis based on highly inaccurate
  wire load models
• With a fixed cell size, the output delay varies with a change in load
  capacitance
• During physical design the output load can be very different from
  the load assumed during synthesis
• Cells must be resized during physical design to accommodate the
  change in load
    Size vs Load - Magma Flow
           Size -vs- Load              Delay




    Size
                                                     Load
                                     Cell delay
                                      is fixed
                        Load


• The Magma flow operates in the "Size vs Load" plane
• The cell delay is fixed based on the applied timing constraints
• The fixed cell delay is expressed in the form of a gain value
• Gain values are assigned during logic synthesis without the need
  of output load estimate; no wire load models are needed
• As the load value changes during physical design, the cell delay
  can be held constant by holding the gain value constant
       Magma's Methodology
                 • Gain Based Optimization
         Super      • Provides logical optimization
         Cells        without wireload models

                 • Fixed Timing Methodology
Gain                 • Establish cell delay budgets
                       during logic synthesis and hold
                       constant through physical design

        Fixed    • Super Cell Library
                     • Describes the cell delay as a
       Timing          function of the gate size, not the
                       output load capacitance
        Gain Based Synthesis
• Synthesis and place-and-route tools should work
  on the same plane.
• A three dimensional space involving size, delay
  and load.
• Logical Effort technique says delay = d*T, where
  ‘d’ is calculated in a slightly complicated manner,
  and T is a process-specific constant, normally
  representing the speed of the basic transistor for
  the technology.
         Gain-Based Synthesis
• d = (LE x G) + p
   – LE – Logical effort
   – G – Gain
   – p – intrinsic delay
• All parameters in calculation of ‘d’ is normalized
  to a base logical function.
• The base function is a inverter driving another
  identical inverter with no parasitics.
Simple delay model of a gate




          Cin    : input capacitance of the gate
          Cgate : the internal parasitic capacitance (mostly diffusion)
          Cload : the external load that the gate is driving
          Rgate : effective output impedance

  Model transistor by a resistor and a switch
  We can assume that the rise-delay and the fall delay are similar.
  Therefore pull-up Rui and pull-down Rdi become Ri
  The transistor impedance depends on the transistor size (W/L)
Gate delay and load




            Delay dependency on
             load is often given as
             table.
With Double the Gate Size :
   Gate delay and size
Assume a gate sizing factor α
 (=relative scaling towards smallest)




               So keeping Cload constant results in:
 Delay and gain
   The gain is the ratio of the
   load capacitance and the
   input capacitance:


   Now we can rewrite the
   previous equations in
   terms of gain:




GAIN IS INDEPENDENT OF THE
      PARASITIC LOAD
Making delay independent of load
If the gain is constant, delay is constant over a range!!
Fixed Timing Methodology
Fixed Timing in a nutshell
 Goal
    Correct by construction (eliminate iterations)
    Emphasis on timing, not on size.

 Map to size-independent supercells
 Pick optimized delay up-front = pick a gain
    If no feasible gain can be found: change your RTL

 Fix this delay throughout placement and routing
 Keep delay constant primarily by cell sizing.
   “Fast circuit design on a napkin”



                     Ivan Sutherland (1991):

                             Delay = (g * h) + p

                                                                     Fixed part,
   Delay of the
                                                                     parasitic delay
   gate + its load

                                                   Electrical effort
                   Logical effort                  proportional to output
                   depends on                      load
                   function of gate                Cload / Cin

For details: See the book: ‘Logical Effort’ by Sutherland, Sproull, Harris Morgan Kaufmann publishers, ISBN 1-55860-557-6
       Structure of Logic Gate
• The figure in next slide illustrates the width of the
  different transistors involved in building basic
  gates, that result in roughly equal output current.
• Each transistor has a capacitance associated
  with it that is a function of its width.
• The mobility of holes is half the mobility of
  electrons
              References
• Logical Effort: Designing Fast CMOS
  circuits – Ivan Sutherland, Bob Sproull and
  David Harris.
Questions and Answers


       Thank You

				
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