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```									CAD for VLSI Design - II

Lecture 5
V. Kamakoti and Shankar Balachandran
Overview of this Lecture
• CMOS Transistor Theory
– Delay Issues
MOSFET Voltages for CMOS
Inverter
Cutoff             Linear            Saturation
VGSn < VTn        VGSn ≥ VTn         VGSn ≥ VTn
Vin ≥ VTn          Vin ≥ VTn
NMO      Vin < VTn
VDSn < VGSn – VTn   VDSn ≥ VGSn – VTn
S
Vout < Vin – VTn    Vout ≥ Vin – VTn

VGSp > VTp       VGSp ≤ VTp           VGSp ≤ VTp
Vin ≤ VTp + VDD      Vin ≤ VTp + VDD
Vin > VTp+ VDD
PMO
VDSp > VGSp – VTp    VDSp ≤ VGSp – VTp
S                     Vout > Vin – VTp     Vout ≤ Vin – VTp
Example: PMOS-NMOS Size Ratio
• For a 0.25μm CMOS process with VDD=2.5V and desired
VM of 1.25V:
VDSATn = 0.63V, VDSATp = -1V, kn’ = 115x10-6 A/V2, kp’ = -
30x10-6 A/V2,
VTn = 0.43V and VTp = -0.4V
(W   L )p     115 × 10 −6 0.63 ( 1.25 − 0.43 − 0.63 2 )
=              ×      ×
(W   L )n     − 30 × 10 −6
− 1.0 ( 2.5 − 1.25 − 0.4 − 1.0 2 )
= 3.5
VM versus Wp /Wn
1.8
•   VM is relatively insensitive to
1.7
Wp/Wn around the center
1.6
point.
1.5
– Small variations of the
1.4                                          ratio do not change the
V (V)

1.3                                          VTC too much. For
M

1.2                                          Wp=2Wn, VM≈1.2V
1.1                                       – Wp can be made only
1                                           2Wn instead of 3.5x or 3x
0.9
saving some valuable
area.
0.8         0                  1
10
Wp/Wn
10     •   Shifting of VTC by changing
the Wn/Wp ratio results in a
characteristics with
VM versus Wp/Wn for 0.25um, 2.5V       asymmetric noise margins.
Effect of Ratio r on Noise Margin

VM             VM
Delays in a Circuit
Sheet Resistance for a 0.25μm
Process
Material       Rs (Ω / □ )
Metal1 (Al)    0.07
Metal5 (Al)    0.04
Polysilicon    20
n+ diffusion   69
p+ diffusion   165
Silicided
9
diffusion
p or n-well    1500
MOSFET Channel Resistance Req
• Req depends strongly on the region of operation.
• For simple performance estimates use approximations:
– Using channel resistance in the linear region

⎛ L⎞                                       1
Req = k ⎜ ⎟             where, k =
⎝W ⎠                               μC ox (VGS − VT )

– Req as the average of the two end points of the transition during
switching. For an NMOSFET switching on in an inverter,
1⎡                           ⎛        V                ⎞⎤
Req =      Ron (V out = V DD ) + Ron ⎜ V out = DD              ⎟⎥
2⎢
⎣                           ⎝         2               ⎠⎦
⎡                                                                 ⎤
1 ⎢⎛ V DS       ⎞                    ⎛ V DS ⎞                       ⎥
= ⎢⎜             ⎟                +   ⎜      ⎟                       ⎥
2⎢ I                                   I DS ⎠                       ⎥
⎢⎝ DS
⎣             ⎠   Vout =V DD       ⎝          Vout =
V DD
2   ⎥
⎦
Req versus VDD
5
x 10
7

6

5
(Ohm)

4
eq

3
R

2

1

0
0 .5           1       1 .5       2   2 .5
V        (V)
DD

Req of a min. size NMOSFET in 0.25μm (VGS=VDD, VDS=VDD→VDD/2)
Source and Drain Resistance
Effects of Resistance
•   Resistance affects performance – RC delay
•   Current supplied through resistive wire IR drop which degrades
signal levels, especially important in the power distribution network
reduces noise margin and changes logic levels as a function of the
distance from the main supply terminals

Reduce distance
Logic                               Logic      between supply
terminal & logic