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					           TFET – a possible replacement for
             CMOS in low-power applications


     Costin Anghel,
     Institut Superieur d'Electronique de Paris
     (Paris, FR)
08/04/2011 Paris              C. ANGHEL           1/25
           Outline:
           • Why do we need another new device?
                   - Power Consumption Problem
                   - CMOS vs. TFET
           • Tunnel FETs
                   - Operation Principle
                   - State-of-the-art
           • Conclusion

08/04/2011 Paris                  C. ANGHEL       2/25
           Outline:
           • Why do we need another new device?
                   - Power Consumption Problem
                   - CMOS vs. TFET
           • Tunnel FETs
                   - Operation Principle
                   - State-of-the-art
           • Conclusion

08/04/2011 Paris                  C. ANGHEL       3/25
                   Power Consumption Problem



   1. Leakage power
      stars to be
      dominant in
      advanced
      technology nodes.

   2. The power per
      chip continues to
      increase.
                                           E.J. Nowak, JRD IBM 2002



08/04/2011 Paris               C. ANGHEL                         4/25
                                        Scaling limited by the 60mV/dec
  Drain Current, I DS (A/ m)



                                 -3
                               10
                        m




                                                     Lower
                                 -5                   V                 • Scaling involves also the scaling of
                               10                    VTt                the threshold voltage (VT).
                                 -7
                               10                                       • The subthreshold slope is limited
                                            Higher                      to a minimum of 60mV/dec for
                               10
                                 -9         IOFF                        CMOS

                                -11
                          10
                                      0.0    0.3     0.6   0.9
                                                                        “Lowering Vt by 60mV increases
                                    Gate Voltage, VGS (V)               the leakage current (power) by 10
                                                                        times.”
  C. HU - 2009                                                          C. HU – 2009


08/04/2011 Paris                                                 C. ANGHEL                                    5/25
                   Sources of Static Power - CMOS:




08/04/2011 Paris                 C. ANGHEL           6/25
Prof. A.M. IONESCU (EPFL) @ ESSDERC 2009
           Outline:
           • Why do we need another new device?
                   - Power Consumption Problem
                   - CMOS vs. TFET
           • Tunnel FETs
                   - Operation Principle
                   - State-of-the-art
           • Conclusion

08/04/2011 Paris                  C. ANGHEL       7/25
                   TFET vs. CMOS

               CMOS                                            TFET
               n-type                                          n-type
                            Oxide                                        Oxide
    Source         Gate    Drain                     Source     Gate    Drain
       n+             i     n+                            p+       i     n+



 CMOS:                                            TFET:
 Pros.: classical device                          Pros.: Extremely Low IOFF
             ION within the ITRS targets                   SS below 60mV/dec
 Cons.: power issue                               Cons.: Low ION
                                                           R&D needed

08/04/2011 Paris                      C. ANGHEL                                8/25
           Outline:
           • Why do we need another new device?
                   - Power Consumption Problem
                   - CMOS vs. TFET
           • Tunnel FETs
                   - Operation Principle
                   - State-of-the-art
           • Conclusion

08/04/2011 Paris                  C. ANGHEL       9/25
                   TFET – the operation principle
                                                     Gate
                                                                    Cutline
                                            Source          Drain

    VG=0V                                     p+        i    n+

    VD=1V
                                       EC
                         Energy [eV]
                                       EV




                                        Location [mm]
08/04/2011 Paris                             C. ANGHEL                   10/25
                   TFET – the operation principle

               TFET        VG=0V                    TFET       VG=1V
               OFF state   VD=1V                    ON state   VD=1V
 Energy [eV]




                                      Energy [eV]
                                                        e-




                  Location [mm]                        Location [mm]
08/04/2011 Paris                   C. ANGHEL                           11/25
           Outline:
           • Why do we need another new device?
                   - Power Consumption Problem
                   - CMOS vs. TFET
           • Tunnel FETs
                   - Operation Principle
                   - State-of-the-art
           • Conclusion

08/04/2011 Paris                  C. ANGHEL       12/25
                   TFET: State-of-the-art – CNTs




J. Appenzeller et al., Phys. Rev. Lett. 93, (2004).
08/04/2011 Paris                       C. ANGHEL      13/25
                   TFET: State-of-the-art – Si




     Choi et al. Electr. Dev. Lett. 28, pp. 743 (2007).
08/04/2011 Paris                        C. ANGHEL         14/25
                   TFET: State-of-the-art – Si




   Second spacer used to create the gate- drain underlapping
   IOFF (~30fA/μm)
   ION (~10-7A/μm)

  F. Mayer et al, IEDM 2008.

08/04/2011 Paris                  C. ANGHEL                15/25
                   TFET: State-of-the-art – DG or GAA




    DG TFET with strained
    Ge heterostructure
    channel:
    ION high but IOFF and VD high

 T. Krishnamohan et al, IEDM 2008.

08/04/2011 Paris                     C. ANGHEL          16/25
                   TFET: State-of-the-art – DG or GAA




         IOFF (~7pA/μm)
         ION (~53mA/μm)
         ION/ IOFF=107
         DIBL = 17mV/V
   Chen et al., IEEE EDL, VOL. 30, p. 754, 2009.

08/04/2011 Paris                         C. ANGHEL      17/25
                   TFET: State-of-the-art – source delta doping




    R. Jhaveri, et. al. TED 01/2011, pp. 80.           K. Jeon, et. al. VLSI, 2010.

08/04/2011 Paris                           C. ANGHEL                                  18/25
                   TFET: State-of-the-art – DG or GAA



   Source heterojunction
   increases the ION
   current

   IOFF current is
   mantained low.




 Anne S. Verhulst et al., IEEE EDL, Vol. 29, pp. 1398, 2008.

08/04/2011 Paris                     C. ANGHEL                 19/25
                   TFET: State-of-the-art – DG or GAA



   Strained Si at the
   Source side –
   increase of ION current

   IOFF current is
   mantained low.




 Kathy Boucart et al., IEEE EDL, Vol. 30, p. 656, 2009

08/04/2011 Paris                     C. ANGHEL           20/25
                   TFET: State-of-the-art – DG or GAA

                                            High k gate dielectrics
                                            - ION current in ITRS
                                            targets
                                            - IOFF current is
                                            mantained low.




     Difficult to integrate
     high k of 100 or 200
     on Si platform…
  Schlosser et al. IEEE TED, vol. 56, p. 100, 2009.
08/04/2011 Paris                      C. ANGHEL                       21/25
                   TFET: State-of-the-art – Spacer Influence

     High-k spacer                     The low-k spacer does not deplete
                                       the source 

                                       Tunneling at the surface of the
                                       device @ highest field 

                                       Increased ION current

     Low-k spacer




                                     Anghel et al. APL, vol. 96, p.122104, 2010.
08/04/2011 Paris                  C. ANGHEL                                 22/25
                                      TFET: Source Position and Film Thickness
                4.50
                               Underlap                    Overlap
                                                                         0.15
                                                                                              tSi=10nm
                4.00
                                               Low-k Spacer Low-k Gate   0.13
                3.50
                                                                         0.11                 Homo-dielectric structures: low ION
                3.00
                                                                                              variation as a function of source position
  ION (mA/mm)




                                                                                ION (nA/mm)
                2.50                                                     0.09


                                                                                              Hetero-dielectric structures: important ION
                2.00        Low-k Spacer High-k Gate                     0.07

                                                                                              variation as a function of source position
                1.50
                                                                         0.05
                1.00
                             High-k Spacer High-k Gate                   0.03
                0.50

                0.00                                                    0.01
                       94       96       98     100      102   104   106

                                     Source Positon - x S (nm)




Hetero-dielectric structures: important ION
variation as a function of tSi



Anghel et al. accepted for publication IEEE TED, 2011.

08/04/2011 Paris                                                          C. ANGHEL                                               23/25
     Conclusion:
     - TFET presents LOW IOFF and LOW ION and SS
     below 60mV/dec.
     - TFET can replace in the future the CMOS for
     low power applications

     Open Question:
     - ITRS LSTP roadmap was built on CMOS,
     should we rethink this roadmap from another
     perspective (i.e. the TFET one)?


08/04/2011 Paris         C. ANGHEL                   24/25
     Many Thanks to:
     - Hraziia, Anju Gupta, Prathyusha Chilagani
     - Prof. Andrei Vladimirescu, Prof. Amara Amara




     Thank you for your attention!




08/04/2011 Paris             C. ANGHEL                25/25

				
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