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					           CDR Readout Board Part1


                  Dave Mercer
                  The University of Manchester




11 October 2002         Dave Mercer The University of Manchester   1
     Part 1 Concerns:-

     • VME Interface and Master FPGA
     • Aux/Internal Bus
     • VME Crate, PSU and Backplane




11 October 2002     Dave Mercer        2
     Recap ReadoutBoard BlockDiagram




11 October 2002    Dave Mercer         3
     Not Shown Explicitly
     •       VME Interruptor capability
         •        All requisite signals are connected to FPGA anyway
         •        Instantiation only needs VHDL code
     •       Extra bussed signals
     •       12.5MHz Clock
     •       Trigger Interface
     •       Logic analyser header
     •       JTAG/ISP from Master to Slave for “loading”
     •       JTAG generally




11 October 2002                             Dave Mercer                4
     Components                     1.


    •        Datapath Bandwidth dictates we use D32 transfers
         •        So J2 is mandatory hence we have the option of A32
         •        + we have 64 (non-bussed) pins
    •        We will use these for LVDS bussed signals
    •        And for hard wired Geographical addressing




11 October 2002                             Dave Mercer                5
     Components                   2.


    •        Aux/Internal bus is not required to be fast therefore
    •        we will only implement a 16bit bus
         •        No byte only transfers
    •        This bus will be a synchronous bus for simplicity
    •        See timing diagram :-




11 October 2002                            Dave Mercer               6
     Aux bus timing




11 October 2002       Dave Mercer   7
     Datapath
     •       Datapath needs to be as fast as possible so I will
     •       implement an asynchronous interface ( if necessary )
         •        12.5Mhz synchronization gives to large a latency
     •       Also BLOCKMODE is necessary to achieve ~30MB/s
         •        ( the Datapath can be read only BUT a slower write diagnostic
         •        Path MUST exist




11 October 2002                             Dave Mercer                           8
     Master FPGA Block Diagram




                                  Total pin count
                                       ~220




11 October 2002     Dave Mercer                     9
     Master FPGA

     •       The only tricky bit is the serial to parallel input circuit
         •        If all 6 Slaves are synchronous to each other then only
         •        One input state machine is needed and the DP RAM is
         •        a single 32 bit wide input RAM.
                  If not then its more complicated and effectively we need
                  6 separate DPRAM’s




11 October 2002                         Dave Mercer                          10
     FPGA Choice
     •       1. Footprint
         •        Choose suitable FBGA (~ 220 I/O pins )
         •        This gives a wide choice of devices for a fixed footprint
     •       2. Technology
         •        Start off with Spartan ( Spartan II needs series 100ohms for
         •        5V compatibility necessary for VME spec. Only go to Virtex
         •        if absolutely necessary.
     •       3. Speed Grade
         •        Answers only after simulation
     •       4 .Manufacturer
         •        Most of the group prefer Xilinx and have the tools




11 October 2002                              Dave Mercer                         11
     Crate and Backplane

     •       “Vanilla “ VME only is needed
         •        ie. NOT VME64x etc.
         However 5V v. 3V3 etc. has to be sorted. There’s
         Probably no room on PCB for DC to DC convertors
         ( at least 6U )
         The extra bussed signals on the J2 connector are not a
             problem but just need to be engineered properly
           EG:-


11 October 2002                         Dave Mercer               12
     Crate and Backplane 2




11 October 2002       Dave Mercer   13

				
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