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Report on modulation and simulation lab
2MDC5 Modeling& Simulation Lab Modeling & simulation Lab RECORD Submitted By : Rakesh Kumar Bazad 1 2MDC5 Modeling& Simulation Lab Experiment No. # 01 Object:-To study the TMS320C6713 processor kit. Equipment Used:-TMS320C6713 DSK. Theory:- INTRODUCTION TO DSP PROCESSORS A signal can be defined as a function that conveys information, generally about the state or behavior of a physical system. There are two basic types of signals viz Analog (continuous time signals which are defined along a continuum of times) and Digital (discrete-time). Remarkably, under reasonable constraints, a continuous time signal can be adequately represented by samples, obtaining discrete time signals. Thus digital signal processing is an ideal choice for anyone who needs the performance advantage of digital manipulation along with today’s analog reality. Hence a processor which is designed to perform the special operations (digital manipulations) on the digital signal within very less time can be called as a Digital signal processor. The difference between a DSP processor, conventional microprocessor and a microcontroller are listed below. Microprocessor or General Purpose Processor such as Intel xx86 or Motorola 680xx family Contains - only CPU -No RAM -No ROM -No I/O ports -No Timer Microcontroller such as 8051 family Contains - CPU - RAM - ROM -I/O ports - Timer & - Interrupt circuitry Some Micro Controllers also contain A/D, D/A and Flash Memory DSP Processors such as Texas instruments and Analog Devices Contains - CPU - RAM -ROM - I/O ports - Timer Optimized for – fast arithmetic - Extended precision - Dual operand fetch - Zero overhead loop - Circular buffering 2 2MDC5 Modeling& Simulation Lab The basic features of a DSP Processor are The C6713™ DSK builds on TI's industry-leading line of low cost, easy-to-use DSP Starter Kit (DSK) development boards. The high-performance board features the TMS320C6713 floating-point DSP. Capable of performing 1350 million floating-point operations per second (MFLOPS), the C6713 DSP makes the C6713 DSK the most powerful DSK development board. The C6713 DSK has a TMS320C6713 DSP onboard that allows full-speed verification of code with Code Composer Studio. The C76713 DSK provides: A USB Interface SDRAM and ROM An analog interface circuit for Data conversion (AIC) An I/O port Embedded JTAG emulation support Connectors on the C6713 DSK provide DSP external memory interface (EMIF) and peripheral signals that enable its functionality to be expanded with custom or third party daughter boards. The DSK provides a C6713 hardware reference design that can assist you in the development of your own C6713-based products. In addition to providing a reference for interfacing the DSP to various types of memories and peripherals, the design also addresses power, clock, JTAG, and parallel peripheral interfaces. The C6711 DSK includes a stereo codec. This analog interface circuit (AIC) has the following characteristics: High-Performance Stereo Codec 90-dB SNR Multibit Sigma-Delta ADC (A-weighted at 48 kHz) 100-dB SNR Multibit Sigma-Delta DAC (A-weighted at 48 kHz) 1.42 V – 3.6 V Core Digital Supply: Compatible With TI C54x DSP Core Voltages 2.7 V – 3.6 V Buffer and Analog Supply: Compatible Both TI C54x DSP Buffer Voltages 8-kHz – 96-kHz Sampling-Frequency Support Software Control Via TI McBSP-Compatible Multiprotocol Serial Port I 2 C-Compatible and SPI-Compatible Serial-Port Protocols Glueless Interface to TI McBSPs Audio-Data Input/OutputVia TI McBSP-Compatible Programmable Audio Interface I 2 S-Compatible Interface Requiring Only One McBSP for both ADC and DAC Standard I 2 S, MSB, or LSB Justified-Data Transfers 16/20/24/32-Bit Word Lengths 3 2MDC5 Modeling& Simulation Lab The C6713DSK has the following features: The 6713 DSK is a low-cost standalone development platform that enables customers to evaluate and develop applications for the TI C67XX DSP family. The DSK also serves as a hardware reference design for the TMS320C6713 DSP. Schematics, logic equations and application notes are available to ease hardware development and reduce time to market. The DSK uses the 32-bit EMIF for the SDRAM (CE0) and daughtercard expansion interface (CE2 and CE3). The Flash is attached to CE1 of the EMIF in 8-bit mode. An on-board AIC23 codec allows the DSP to transmit and receive analog signals. McBSP0 is used for the codec control interface and McBSP1 is used for data. Analog audio I/O is done through four 3.5mm audio jacks that correspond to microphone input, line input, line output and headphone output. The codec can select the microphone or the line input as the active input. The analog output is driven to both the line out (fixed gain) and headphone (adjustable gain) connectors. McBSP1 can be re- routed to the expansion connectors in software. A programmable logic device called a CPLD is used to implement glue logic that ties the board components together. The CPLD has a register based user interface that lets the user configure the board by reading and writing to the CPLD registers. The registers reside at the midpoint of CE1. The DSK includes 4 LEDs and 4 DIPswitches as a simple way to provide the user with interactive feedback. Both are accessed by reading and writing to the CPLD registers. An included 5V external power supply is used to power the board. On-board voltage regulators provide the 1.26V DSP core voltage, 3.3V digital and 3.3V analog voltages. A voltage supervisor monitors the internally generated voltage, and will hold the board in reset until the supplies are within operating specifications and the reset button is released. If desired, JP1 and JP2 can be used as power test points for the core and I/O power supplies. Code Composer communicates with the DSK through an embedded JTAG emulator with a USB host interface. The DSK can also be used with an external emulator through the external JTAG connector. TMS320C6713 DSP Features Highest-Performance Floating-Point Digital Signal Processor (DSP): Eight 32-Bit Instructions/Cycle 32/64-Bit Data Word 300-, 225-, 200-MHz (GDP), and 225-, 200-, 167-MHz (PYP) Clock Rates 3.3-, 4.4-, 5-, 6-Instruction Cycle Times 2400/1800, 1800/1350, 1600/1200, and 1336/1000 MIPS /MFLOPS Rich Peripheral Set, Optimized for Audio Highly Optimized C/C++ Compiler Extended Temperature Devices Available Advanced Very Long Instruction Word (VLIW) TMS320C67x™ DSP Core Eight Independent Functional Units: Two ALUs (Fixed-Point) Four ALUs (Floating- and Fixed-Point) Two Multipliers (Floating- and Fixed-Point) Load-Store Architecture With 32 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size 4 2MDC5 Modeling& Simulation Lab All Instructions Conditional Instruction Set Features Native Instructions for IEEE 754 Single- and Double-Precision Byte-Addressable (8-, 16-, 32-Bit Data) 8-Bit Overflow Protection Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization L1/L2 Memory Architecture 4K-Byte L1P Program Cache (Direct-Mapped) 4K-Byte L1D Data Cache (2-Way) 256K-Byte L2 Memory Total: 64K-Byte L2 Unified Cache/Mapped RAM, and 192K-Byte Additional L2 Mapped RAM Device Configuration Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot Endianness: Little Endian, Big Endian 32-Bit External Memory Interface (EMIF) Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM 512M-Byte Total Addressable External Memory Space Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels) 16-Bit Host-Port Interface (HPI) Two Multichannel Audio Serial Ports (McASPs) Two Independent Clock Zones Each (1 TX and 1 RX) Eight Serial Data Pins Per Port: Individually Assignable to any of the Clock Zones Each Clock Zone Includes: Programmable Clock Generator Programmable Frame Sync Generator TDM Streams From 2-32 Time Slots Support for Slot Size: 8, 12, 16, 20, 24, 28, 32 Bits Data Formatter for Bit Manipulation Wide Variety of I2S and Similar Bit Stream Formats Integrated Digital Audio Interface Transmitter (DIT) Supports: S/PDIF, IEC60958-1, AES-3, CP-430 Formats Up to 16 transmit pins Enhanced Channel Status/User Data Extensive Error Checking and Recovery Two Inter-Integrated Circuit Bus (I2C Bus™) Multi-Master and Slave Interfaces Two Multichannel Buffered Serial Ports: Serial-Peripheral-Interface (SPI) High-Speed TDM Interface AC97 Interface Two 32-Bit General-Purpose Timers Dedicated GPIO Module With 16 pins (External Interrupt Capable) Flexible Phase-Locked-Loop (PLL) Based Clock Generator Module IEEE-1149.1 (JTAG ) Boundary-Scan-Compatible Package Options: 208-Pin PowerPAD™ Plastic (Low-Profile) Quad Flatpack (PYP) 5 2MDC5 Modeling& Simulation Lab 272-BGA Packages (GDP and ZDP) 0.13-µm/6-Level Copper Metal Process CMOS Technology 3.3-V I/Os, 1.2 -V Internal (GDP & PYP) 3.3-V I/Os, 1.4-V Internal (GDP)(300 MHz only) TMS320C6713 DSK Overview Block Diagram 6 2MDC5 Modeling& Simulation Lab Experiment No. # 02 AIM:- To verify Linear Convolution. EQUIPMENTS:- TMS 320C6713 Kit THEORY Convolution is a formal mathematical operation, just as multiplication, addition, and integration. Addition takes two numbers and produces a third number, while convolution takes two signals and produces a third signal. Convolution is used in the mathematics of many fields, such as probability and statistics. In linear systems, convolution is used to describe the relationship between three signals of interest: the input signal, the impulse response, and the output signal. In this equation, x1(k), x2 (n-k) and y(n) represent the input to and output from the system at time n. Here we could see that one of the input is shifted in time by a value everytime it is multiplied with the other input signal. Linear Convolution is quite often used as a method of implementing filters of various types. ALGORITHM Step 1 Declare three buffers namely Input buffer, Temporary Buffer, Output Buffer. Step 2 Get the input from the CODEC, store it in Input buffer and transfer it to the first location of the Temporary buffer. Step 3 Make the Temporary buffer to point to the last location. Step 4 Multiply the temporary buffer with the coefficients in the data memory and accumulate it with the previous output. Step 5 Store the output in the output buffer. Step 6 Repeat the steps from 2 to 5. PROGRAM #include<stdio.h> intx[15],h[15],y[15]; main() { inti,j,m,n; printf("\n enter value for m"); scanf("%d",&m); printf("\n enter value for n"); scanf("%d",&n); printf("Enter values for i/p\n"); for(i=0;i<m;i++) scanf("%d",&x[i]); printf("Enter Values for n \n"); for(i=0;i<n;i++) scanf("%d",&h[i]); for(i=m;i<=m+n-1;i++) x[i]=0; for(i=n;i<=m+n-1;i++) h[i]=0; 7 2MDC5 Modeling& Simulation Lab for(i=0;i<m+n-1;i++) { y[i]=0; for(j=0;j<=i;j++) { y[i]=y[i]+(x[j]*h[i-j]); } } for(i=0;i<m+n-1;i++) printf("\n The Value of output y[%d]=%d",i,y[i]); } Result: enter value for m4 enter value for n4 Enter values for i/p 1234 Enter Values for n 1234 The Value of output y[0]=1 The Value of output y[1]=4 The Value of output y[2]=10 The Value of output y[3]=20 The Value of output y[4]=25 The Value of output y[5]=24 The Value of output y[6]=16 8 2MDC5 Modeling& Simulation Lab Experiment No. # 03 AIM:-To verify Circular Convolution. EQUIPMENTS USED:-DSK TMS320C6713 THEORY Circular convolution is another way of finding the convolution sum of two input signals. It resembles the linear convolution, except that the sample values of one of the input signals is folded and right shifted before the convolution sum is found. Also note that circular convolution could also be found by taking the DFT of the two input signals and finding the product of the two frequency domain signals. The Inverse DFT of the product would give the output of the signal in the time domain which is the circular convolution output. The two input signals could have been of varying sample lengths. But we take the DFT of higher point, which ever signals levels to. For eg. If one of the signal is of length 256 and the other spans 51 samples, then we could only take 256 point DFT. So the output of IDFT would be containing 256 samples instead of 306 samples, which follows N1+N2 – 1 where N1 & N2 are the lengths 256 and 51 respectively of the two inputs. Thus the output which should have been 306 samples long is fitted into 256 samples. The 256 points end up being a distorted version of the correct signal. This process is called circular convolution. PROGRAM: /* prg to implement circular convolution */ #include<stdio.h> intm,n,x[30],h[30],y[30],i,j,temp[30],k,x2[30],a[30]; void main() { printf(" enter the length of the first sequence\n"); scanf("%d",&m); printf(" enter the length of the second sequence\n"); scanf("%d",&n); printf(" enter the first sequence\n"); for(i=0;i<m;i++) scanf("%d",&x[i]); printf(" enter the second sequence\n"); for(j=0;j<n;j++) scanf("%d",&h[j]); if(m-n!=0) /*If length of both sequences are not equal*/ { if(m>n) /* Pad the smaller sequence with zero*/ { for(i=n;i<m;i++) h[i]=0; n=m; } for(i=m;i<n;i++) x[i]=0; m=n; } 9 2MDC5 Modeling& Simulation Lab y[0]=0; a[0]=h[0]; for(j=1;j<n;j++) /*folding h(n) to h(-n)*/ a[j]=h[n-j]; /*Circular convolution*/ for(i=0;i<n;i++) y[0]+=x[i]*a[i]; for(k=1;k<n;k++) { y[k]=0; /*circular shift*/ for(j=1;j<n;j++) x2[j]=a[j-1]; x2[0]=a[n-1]; for(i=0;i<n;i++) { a[i]=x2[i]; y[k]+=x[i]*x2[i]; } } /*displaying the result*/ printf(" the circular convolution is\n"); for(i=0;i<n;i++) printf("%d \t",y[i]); } OUTPUT:- Enter the first sequence 5 6 7 Enter the second sequence 7 8 5 4 OUTPUT ;- the circular convolution is 94 110 122 106 10 2MDC5 Modeling& Simulation Lab Model Graph:- 11 2MDC5 Modeling& Simulation Lab Experiment No. # 004 AIM:-To find the Fast Fourier Transform for the realtime samples. EQUIPMENT USED:- TMS320C6713 DSK. THEORY The Fast Fourier Transform is useful to map the time-domain sequence into a continuous function of a frequency variable. The FFT of a sequence {x(n)} of length N is given by a complex-valued sequence X(k). M nk j 2 X (k ) x(n) e n ;0 k N 1 k 0 The above equation is the mathematical representation of the DFT. As the number of computations involved in transforming a N point time domain signal into its corresponding frequency domain signal was found to be N2 complex multiplications, an alternative algorithm involving lesser number of computations is opted. When the sequence x(n) is divided into 2 sequences and the DFT performed separately, the resulting number of computations would be N2/2 (i.e.) N2 N2 21 21 x(k ) x(2n) WN nk x(2n 1) WN2 n1) k 2 ( (6) n 0 n 0 Consider x(2n) be the even sample sequences and x(2n+1) be the odd sample sequence derived form x(n). N2 21 x ( 2n) n 0 2 WN nk ] would result in (7) N2 21 (N/2)2multiplication’s x(2n 1) n 0 WN2 n1) k ( (8) an other (N/2)2 multiplication's finally resulting in (N/2)2 + (N/2)2 12 2MDC5 Modeling& Simulation Lab N2 N2 N2 = 4 4 2 Computatio ns Further solving Eg. (2) N2 N 21 21 k x(k ) x(2n) W 2 nk N x(2n 1) W ( 2 nk ) N W (9) N n 0 n0 N N 21 k 21 x(2n) W 2 nk N W x(2n 1) WN2 nk ) (10) ( N n0 n0 Dividing the sequence x(2n) into further 2 odd and even sequences would reduce the computations. WN is the twiddle factor j 2 e n j 2 nk W nk N e n N N K K W N 2 WN W N 2 (11) j 2 j 2 n k e n e n 2 j 2 k W k N e n WN (cos j sin ) k 13 2MDC5 Modeling& Simulation Lab N K W N 2 WN (1) k N K W N 2 WN k (12) Employing this equation, we deduce N2 N 21 21 x(k ) x(2n) WN nk x(2n 1) WN2 nk ) (13) 2 ( n0 n0 N 21 K N N x(k ) x(2n) WN W x(2n 1) 21 WN2 nk ) (14) 2 nk ( 2 n 0 N The time burden created by this large number of computations limits the usefulness of DFT in many applications. Tremendous efforts devoted to develop more efficient ways of computing DFT resulted in the above explained Fast Fourier Transform algorithm. This mathematical shortcut reduces the number of calculations the DFT requires drastically. The above mentioned radix-2 decimation in time FFT is employed for domain transformation. Dividing the DFT into smaller DFTs is the basis of the FFT. A radix-2 FFT divides the DFT into two smaller DFTs, each of which is divided into smaller DFTs and so on, resulting in a combination of two-point DFTs. The Decimation -In-Time (DIT) FFT divides the input (time) sequence into two groups, one of even samples and the other of odd samples. N/2 point DFT are performed on the these sub-sequences and their outputs are combined to form the N point DFT. FIG. 3A.1 The above shown mathematical representation forms the basis of N point FFT and is called theButterfly Structure. 14 2MDC5 Modeling& Simulation Lab STAGE – I STAGE - II STAGE – III FIG. 3A.2 – 8 POINT DIT 15 2MDC5 Modeling& Simulation Lab ALGORITHM Step 1 sample the input (N) of any desired frequency. Convert it to fixed-point format and scale the input to avoid overflow during manipulation. Step 2 Declare four buffers namely real input, real exponent, imaginary exponent and imaginary input. Step 3 Declare three counters for stage, group and butterfly. Step 4 Implement the Fast Fourier Transform for the input signal. Step 5 Store the output (Real and Imaginary) in the output buffer. Step 6 Decrement the counter of butterfly. Repeat from the Step 4 until the counter reaches zero. Step 7 If the butterfly counter is zero, modify the exponent value. Step 8 Repeat from the Step 4 until the group counter reaches zero. Step 9 If the group counter is zero, multiply the butterfly value by two and divide the group value by two. Step 10 Repeat from the Step 4 until the stage counter reaches zero. Step 11 Transmit the FFT output through line out port. PROGRAM: - #include <math.h> #define PTS 128 //# of points for FFT #define PI 3.14159265358979 typedefstruct {float real,imag;} COMPLEX; voidFFT(COMPLEX *Y, int n); //FFT prototype floatiobuffer[PTS]; //as input and output buffer float x1[PTS],x[PTS]; //intermediate buffer short i; //general purpose index variable shortbuffercount = 0; //number of new samples in iobuffer short flag = 0; //set to 1 by ISR when iobuffer full float y[128]; COMPLEX w[PTS]; //twiddle constants stored in w COMPLEX samples[PTS]; //primary working buffer main() { floatj,sum=0.0 ; intn,k,i,a; for (i = 0 ; i<PTS ; i++) // set up twiddle constants in w { w[i].real = cos(2*PI*i/(PTS*2.0)); //Re component of twiddle constants w[i].imag =-sin(2*PI*i/(PTS*2.0)); /*Im component of twiddle constants*/ } 16 2MDC5 Modeling& Simulation Lab /****************InputSignalX(n)***************************************/ for(i=0,j=0;i<PTS;i++) { x[i] = sin(2*PI*5*i/PTS); // Signal x(Fs)=sin(2*pi*f*i/Fs); samples[i].real=0.0; samples[i].imag=0.0; } /********************** FFT of R(t) *****************************/ for (i = 0 ; i < PTS ; i++) //swap buffers { samples[i].real=iobuffer[i]; //buffer with new data } for (i = 0 ; i < PTS ; i++) samples[i].imag = 0.0; //imag components = 0 FFT(samples,PTS); //call function FFT.c /******************** PSD *******************************************/ for (i = 0 ; i < PTS ; i++) //compute magnitude { x1[i] = sqrt(samples[i].real*samples[i].real + samples[i].imag*samples[i].imag); } } //end of main void FFT(COMPLEX *Y, int N) //input sample array, # of points { COMPLEX temp1,temp2; //temporary storage variables inti,j,k; //loop counter variables intupper_leg, lower_leg; //index of upper/lower butterfly leg intleg_diff; //difference between upper/lower leg intnum_stages = 0; //number of FFT stages (iterations) int index, step; //index/step through twiddle constant i = 1; //log(base2) of N points= # of stages do { num_stages +=1; i = i*2; }while (i!=N); leg_diff = N/2; //difference between upper&lower legs step = (PTS*2)/N; //step between values in twiddle.h // 512 17 2MDC5 Modeling& Simulation Lab for (i = 0;i <num_stages; i++) //for N-point FFT { index = 0; for (j = 0; j <leg_diff; j++) { for (upper_leg = j; upper_leg< N; upper_leg += (2*leg_diff)) { lower_leg = upper_leg+leg_diff; temp1.real = (Y[upper_leg]).real + (Y[lower_leg]).real; temp1.imag = (Y[upper_leg]).imag + (Y[lower_leg]).imag; temp2.real = (Y[upper_leg]).real - (Y[lower_leg]).real; temp2.imag = (Y[upper_leg]).imag - (Y[lower_leg]).imag; (Y[lower_leg]).real = temp2.real*(w[index]).real -temp2.imag*(w[index]).imag; (Y[lower_leg]).imag = temp2.real*(w[index]).imag +temp2.imag*(w[index]).real; (Y[upper_leg]).real = temp1.real; (Y[upper_leg]).imag = temp1.imag; } index += step; } leg_diff = leg_diff/2; step *= 2; } j = 0; for (i = 1; i < (N-1); i++) //bit reversal for resequencing data { k = N/2; while (k <= j) { j = j - k; k = k/2; } j = j + k; if (i<j) { temp1.real = (Y[j]).real; temp1.imag = (Y[j]).imag; (Y[j]).real = (Y[i]).real; (Y[j]).imag = (Y[i]).imag; (Y[i]).real = temp1.real; (Y[i]).imag = temp1.imag; } } return; } 18 2MDC5 Modeling& Simulation Lab OUTPUT: DFT or FFT spectrum of sinusoidal signal f= 10 Hz 19 2MDC5 Modeling& Simulation Lab Experiment No.#05 AIM: - To design and implement a low pass FIR filter using windowing technique. APPARATUS USED: - TMS320C6713 DSK THEORY: - A Finite Impulse Response (FIR) filter is a discrete linear time-invariant system whose output is based on the weighted summation of a finite number of past inputs. An FIR transversal filter structure can be obtained directly from the equation for discrete-time convolution. N 1 y ( n) x ( k ) h( n k ) 0 n N 1 (1) k 0 In this equation, x(k) and y(n) represent the input to and output from the filter at time n. h(n-k) is the transversal filter coefficients at time n. These coefficients are generated by using FDS (Filter Design Software or Digital filter design package). Window Function A desirable property of the window function is that the function is of finite duration in the time domain and that the Fourier transform has maximum energy in the main lobe or a given peak side lobe amplitude. Kaiser Window In a Kaiser window the side lobe level can be controlled with respect to the main lobe peak by varying a parameter, α. The Kaiser window function is given by Where & are the Bessel functions The actual pass band ripple Ap and minimum stop band attenuation As are given by dB -20 l δs dB 20 2MDC5 Modeling& Simulation Lab δ=min(δp, δs) From the Kaiser design equation Order of the filter can be find from the equation Where the parameter D is The impulse response is computed from for Low Pass FIR Filter Where , and The procedures of designing FIR filters using windows are summarized as follows: 1. Determine the window type that will satisfy the stop band attenuation requirement. 2. Determine the window size L based on the given transition width. 3. Calculate the window coefficient w(n), n=0,1……, L-1. 4. Generate the ideal impulse response h(n), that is for the desired filter. 5. Truncate the ideal impulse response of an infinite length to obtain h’(n), -M≤n≤M. 6. Make the filter casual by shifting the result M units to the right to obtain b’l, l=0,1….., L-1. 7. Multiply the window coefficients and the impulse response coefficients obtained in (step 6) sample by sample. That is, bl=b’l*w(l), l=0,1…., L-1. 21 2MDC5 Modeling& Simulation Lab FLOW CHART TO IMPLEMENT FIR FILTER: Start Initialize the DSP Board. Take a new input in ‘data’ from the analog in of codec in ‘data’ Initialize Counter = 0 Initialize Output = 0 ,i = 0 Output += coeff[N-i]*val[i] Shift the input value by one No Is the loop Cnt = order Poll the ready bit, when Yes asserted proceed. Output += coeff[0]*data Put the ‘data’ in ‘val’ array. Write the value ‘Output’ to Analog output of the codec 22 2MDC5 Modeling& Simulation Lab C PROGRAM TO IMPLEMENT FIR FILTER: #include "filtercfg.h" #include "dsk6713.h" #include "dsk6713_aic23.h" floatfilter_Coeff[] ={0.000000,-0.001591,-0.002423,0.000000,0.005728, 0.011139,0.010502,-0.000000,-0.018003,-0.033416,-0.031505,0.000000, 0.063010,0.144802,0.220534,0.262448,0.220534,0.144802,0.063010,0.000000, -0.031505,-0.033416,-0.018003,-0.000000,0.010502,0.011139,0.005728, 0.000000,-0.002423,-0.001591,0.000000 }; static short in_buffer[100]; DSK6713_AIC23_Config config = {\ 0x0017, /* 0 DSK6713_AIC23_LEFTINVOL Leftline input channel volume */\ 0x0017, /* 1 DSK6713_AIC23_RIGHTINVOL Right line input channel volume*/\ 0x00d8, /* 2 DSK6713_AIC23_LEFTHPVOL Left channel headphone volume */\ 0x00d8, /* 3 DSK6713_AIC23_RIGHTHPVOL Right channel headphone volume */\ 0x0011, /* 4 DSK6713_AIC23_ANAPATH Analog audio path control */\ 0x0000, /* 5 DSK6713_AIC23_DIGPATH Digital audio path control */\ 0x0000, /* 6 DSK6713_AIC23_POWERDOWN Power down control */\ 0x0043, /* 7 DSK6713_AIC23_DIGIF Digital audio interface format */\ 0x0081, /* 8 DSK6713_AIC23_SAMPLERATE Sample rate control */\ 0x0001 /* 9 DSK6713_AIC23_DIGACT Digital interface activation */ \ }; /* * main() - Main code routine, initializes BSL and generates tone */ void main() { DSK6713_AIC23_CodecHandle hCodec; Uint32 l_input, r_input,l_output, r_output; /* Initialize the board support library, must be called first */ DSK6713_init(); /* Start the codec */ hCodec = DSK6713_AIC23_openCodec(0, &config); DSK6713_AIC23_setFreq(hCodec, 1); while(1) { /* Read a sample to the left channel */ while (!DSK6713_AIC23_read(hCodec, &l_input)); /* Read a sample to the right channel */ while (!DSK6713_AIC23_read(hCodec, &r_input)); l_output=(Int16)FIR_FILTER(&filter_Coeff ,l_input); r_output=l_output; /* Send a sample to the left channel */ while (!DSK6713_AIC23_write(hCodec, l_output)); 23 2MDC5 Modeling& Simulation Lab /* Send a sample to the right channel */ while (!DSK6713_AIC23_write(hCodec, r_output)); } /* Close the codec */ DSK6713_AIC23_closeCodec(hCodec); } signedint FIR_FILTER(float * h, signed int x) { int i=0; signed long output=0; in_buffer[0] = x; /* new input at buffer[0] */ for(i=30;i>0;i--) in_buffer[i] = in_buffer[i-1]; /* shuffle the buffer */ for(i=0;i<32;i++) output = output + h[i] * in_buffer[i]; return(output); } 24 2MDC5 Modeling& Simulation Lab Experiment No. # 06 AIM:-To design and implement a low pass IIR filter using windowing technique. APPARATUS USED: -TMS320C6713 DSK. THEORY: - The IIR filter can realize both the poles and zeroes of a system because it has a rational transfer function, described by polynomials in z in both the numerator and the denominator: M b k 0 k z k H ( z) N (2) a k 1 k Z k The difference equation for such a system is described by the following: M N y ( n) bk x ( n k ) a k y (n k ) (3) k 0 k 1 M and N are order of the two polynomials bk andak are the filter coefficients. These filter coefficients are generated using FDS (Filter Design software or Digital Filter design package). GENERAL CONSIDERATIONS: In the design of frequency – selective filters, the desired filter characteristics are specified in the frequency domain in terms of the desired magnitude and phase response of the filter. In the filter design process, we determine the coefficients of a causal IIR filter that closely approximates the desired frequency response specifications. IMPLEMENTATION OF DISCRETE-TIME SYSTEMS: Discrete time Linear Time-Invariant (LTI) systems can be described completely by constant coefficient linear difference equations. Representing a system in terms of constant coefficient linear difference equation is it’s time domain characterization. In the design of a simple frequency–selective filter, we would take help of some basic implementation methods for realizations of LTI systems described by linear constant coefficient difference equation. BACKGROUND CONCEPTS: An Infinite impulse response (IIR) filter possesses an output response to an impulse which is of an infinite duration. The impulse response is "infinite" since there is feedback in the filter, that is if you put in an impulse ,then its output must produced for infinite duration of time. 25 2MDC5 Modeling& Simulation Lab ALGORITHM TO IMPLEMENT: We need to realize the Butter worth band pass IIR filter by implementing the difference equation y[n] = b0x[n] + b1x[n-1]+b2x[n-2]-a1y[n-1]-a2y[n-2] where b0 – b2, a0-a2 are feed forward and feedback word coefficients respectively [Assume 2nd order of filter].These coefficients are calculated using MATLAB.A direct form I implementation approach is taken. Step 1 - Initialize the McBSP, the DSP board and the on board codec. “Kindly refer the Topic Configuration of 6713Codec using BSL” Step 2 - Initialize the discrete time system , that is , specify the initial conditions. Generally zero initial conditions are assumed. Step 3 - Take sampled data from codec while input is fed to DSP kit from the signal generator. Since Codec is stereo , take average of input data read from left and right channel . Store sampled data at a memory location. Step 4 - Perform filter operation using above saiddifference equation and store filter Output at a memory location . Step 5 - Output the value to codec (left channel and right channel) and view the output at Oscilloscope. Step 6 - Go to step 3. FLOWCHART FOR IIR IMPLEMENTATION: Start Initialize the DSP Board. Set initial conditions of discrete time system by making x[0]-x[2] and y[0]- y[2] equal to zeros and a0-a2,b0-b2 with MATLAB filter coefficients Take a new input and store it in x[0]. Do y[-3] = y[-2],y[-2]=y[-1] output = x[0]b0+x[-1]b1+ and Y[-1] = output . x[-2]b2 - y[-1]a1 - y[-2]a2 x[-3] = x[-2], x[-2]=x[-1] x[-1]=x[0] Write ‘output’ to analogi/o. Poll for ready bit Flowchart Pollimplementing IIR filter. for the ready bit, when asserted Stop proceed. 26 2MDC5 Modeling& Simulation Lab MATLAB PROGRAM TO GENRATE FILTER CO-EFFICIENTS % IIR Low pass Butterworth and Chebyshev filters % sampling rate - 24000 order = 2; cf=[2500/12000,8000/12000,1600/12000]; % cutoff frequency - 2500 [num_bw1,den_bw1]=butter(order,cf(1)); [num_cb1,den_cb1]=cheby1(order,3,cf(1)); % cutoff frequency - 8000 [num_bw2,den_bw2]=butter(order,cf(2)); [num_cb2,den_cb2]=cheby1(order,3,cf(2)); fid=fopen('IIR_LP_BW.txt','wt'); fprintf(fid,'\t\t-----------Pass band range: 0-2500Hz----------\n'); fprintf(fid,'\t\t-----------Magnitude response: Monotonic-----\n\n\'); fprintf(fid,'\n float num_bw1[9]={'); fprintf(fid,'%f,%f,%f,%f,%f,\n%f,%f,%f,%f};\n',num_bw1); fprintf(fid,'\nfloat den_bw1[9]={'); fprintf(fid,'%f,%f,%f,%f,%f,\n%f,%f,%f,%f};\n',den_bw1); fprintf(fid,'\n\n\n\t\t-----------Pass band range: 0-8000Hz----------\n'); fprintf(fid,'\t\t-----------Magnitude response: Monotonic-----\n\n'); fprintf(fid,'\nfloat num_bw2[9]={'); fprintf(fid,'%f,%f,%f,%f,%f,\n%f,%f,%f,%f};\n',num_bw2); fprintf(fid,'\nfloat den_bw2[9]={'); fprintf(fid,'%f,%f,%f,%f,%f,\n%f,%f,%f,%f};\n',den_bw2); fclose(fid); winopen('IIR_LP_BW.txt'); fid=fopen('IIR_LP_CHEB Type1.txt','wt'); fprintf(fid,'\t\t-----------Pass band range: 2500Hz----------\n'); fprintf(fid,'\t\t-----------Magnitude response: Rippled (3dB) -----\n\n\'); fprintf(fid,'\nfloat num_cb1[9]={'); fprintf(fid,'%f,%f,%f,%f,%f,\n%f,%f,%f,%f};\n',num_cb1); fprintf(fid,'\nfloat den_cb1[9]={'); fprintf(fid,'%f,%f,%f,%f,%f,\n%f,%f,%f,%f};\n',den_cb1); fprintf(fid,'\n\n\n\t\t-----------Pass band range: 8000Hz----------\n'); fprintf(fid,'\t\t-----------Magnitude response: Rippled (3dB)-----\n\n'); fprintf(fid,'\nfloat num_cb2[9]={'); fprintf(fid,'%f,%f,%f,%f,%f,\n%f,%f,%f,%f};\n',num_cb2); fprintf(fid,'\nfloat den_cb2[9]={'); fprintf(fid,'%f,%f,%f,%f,%f,\n%f,%f,%f,%f};\n',den_cb2); fclose(fid); winopen('IIR_LP_CHEB Type1.txt'); %%%%%%%%%%%%%%%%%% figure(1); [h,w]=freqz(num_bw1,den_bw1); w=(w/max(w))*12000; plot(w,20*log10(abs(h)),'linewidth',2) hold on [h,w]=freqz(num_cb1,den_cb1); w=(w/max(w))*12000; plot(w,20*log10(abs(h)),'linewidth',2,'color','r') grid on 27 2MDC5 Modeling& Simulation Lab legend('Butterworth','Chebyshev Type-1'); xlabel('Frequency in Hertz'); ylabel('Magnitude in Decibels'); title('Magnitude response of Low pass IIR filters (Fc=2500Hz)'); figure(2); [h,w]=freqz(num_bw2,den_bw2); w=(w/max(w))*12000; plot(w,20*log10(abs(h)),'linewidth',2) hold on [h,w]=freqz(num_cb2,den_cb2); w=(w/max(w))*12000; plot(w,20*log10(abs(h)),'linewidth',2,'color','r') grid on legend('Butterworth','Chebyshev Type-1 (Ripple: 3dB)'); xlabel('Frequency in Hertz'); ylabel('Magnitude in Decibels'); title('Magnitude response in the passband'); axis([0 12000 -20 20]); IIR_CHEB_LP FILTER CO-EFFICIENTS: Co- Fc=2500Hz Fc=800Hz Fc=8000Hz Effic Floating Point Fixed Point Floating Point Fixed Point Floating Point Fixed Point ient Values Values(Q15) Values Values(Q15 Values Values(Q15) s ) B0 0.044408 1455 0.005147 168 0.354544 11617 B1 0.088815 1455[B1/2] 0.010295 168[B1/2] 0.709088 11617[B1/2] B2 0.044408 1455 0.005147 168 0.354544 11617 A0 1.000000 32767 1.000000 32767 1.000000 32767 A1 -1.412427 -23140[A1/2] -1.844881 -30225[A1/2] 0.530009 8683[A1/2] A2 0.663336 21735 0.873965 28637 0.473218 15506 15 Note: We have Multiplied Floating Point Values with 32767(2 ) to get Fixed Point Values. IIR_BUTTERWORTH_LP FILTER CO-EFFICIENTS: Co- Fc=2500Hz Fc=800Hz Fc=8000Hz Effic Floating Point Fixed Point Floating Point Fixed Point Floating Point Fixed Point ient Values Values(Q15) Values Values(Q15 Values Values(Q15) s ) B0 0.072231 2366 0.009526 312 0.465153 15241 B1 0.144462 2366[B1/2] 0.019052 312[B1/2] 0.930306 15241[B1/2] B2 0.072231 2366 0.009526 312 0.465153 15241 A0 1.000000 32767 1.000000 32767 1.000000 32767 A1 -1.109229 -18179[A1/2] -1.705552, -27943[A1/2] 0.620204 10161[A1/2] A2 0.398152 13046 0.743655 24367 0.240408 7877 15 Note: We have Multiplied Floating Point Values with 32767(2 ) to get Fixed Point Values. IIR_CHEB_HP FILTER CO-EFFICIENTS: 28 2MDC5 Modeling& Simulation Lab Co- Fc=2500Hz Fc=4000Hz Fc=7000Hz Effi Floating Point Fixed Point Floating Fixed Point Floating Point Fixed Point cien Values Values(Q15) Point Values Values(Q1 Values Values(Q15) ts 5) B0 0.388513 12730 0.282850 9268 0.117279 3842 B1 -0.777027 -12730[B1/2] -0.565700 -9268[B1/2] -0.234557 -3842[B1/2] B2 0.388513 12730 0.282850 9268 0.117279 3842 A0 1.000000 32767 1.000000 32767 1.000000 32767 A1 -1.118450 -18324[A1/2] -0.451410 -7395[A1/2] 0.754476 12360[A1/2] A2 0.645091 21137 0.560534 18367 0.588691 19289 15 Note: We have Multiplied Floating Point Values with 32767(2 ) to get Fixed Point Values. IIR_BUTTERWORTH_HP FILTER CO-EFFICIENTS: Co- Fc=2500Hz Fc=4000Hz Fc=7000Hz Effi Floating Point Fixed Point Floating Fixed Point Floating Point Fixed Point cien Values Values(Q15) Point Values Values(Q15 Values Values(Q15) ts ) B0 0.626845 20539 0.465153 15241 0.220195 7215 B1 -1.253691 -20539[B1/2] -0.930306 - -0.440389 -7215[B1/2] 15241[B1/2] B2 0.626845 20539 0.465153 15241 0.220195 7215 A0 1.000000 32767 1.000000 32767 1.000000 32767 A1 -1.109229 -18173[A1/2] -0.620204 - 0.307566 5039[A1/2} 10161[A1/2] A2 0.398152 13046 0.240408 7877 0.188345 6171 15 Note: We have Multiplied Floating Point Values with 32767(2 ) to get Fixed Point Values. ‘C’ PROGRAM TO IMPLEMENT IIR FILTER #include "filtercfg.h" #include "dsk6713.h" #include "dsk6713_aic23.h" const signed intfilter_Coeff[] = { //12730,-12730,12730,2767,-18324,21137 /*HP 2500 */ //312,312,312,32767,-27943,24367 /*LP 800 */ //1455,1455,1455,32767,-23140,21735 /*LP 2500 */ //9268,-9268,9268,32767,-7395,18367 /*HP 4000*/ 7215,-7215,7215,32767,5039,6171, /*HP 7000*/ } ; /* Codec configuration settings */ DSK6713_AIC23_Config config = { \ 0x0017, /* 0 DSK6713_AIC23_LEFTINVOL Left line input channel volume */ \ 0x0017, /* 1 DSK6713_AIC23_RIGHTINVOL Right line input channel volume */\ 0x00d8, /* 2 DSK6713_AIC23_LEFTHPVOL Left channel headphone volume */ \ 0x00d8, /* 3 DSK6713_AIC23_RIGHTHPVOL Right channel headphone volume */ \ 29 2MDC5 Modeling& Simulation Lab 0x0011, /* 4 DSK6713_AIC23_ANAPATH Analog audio path control */ \ 0x0000, /* 5 DSK6713_AIC23_DIGPATH Digital audio path control */ \ 0x0000, /* 6 DSK6713_AIC23_POWERDOWN Power down control */ \ 0x0043, /* 7 DSK6713_AIC23_DIGIF Digital audio interface format */ \ 0x0081, /* 8 DSK6713_AIC23_SAMPLERATE Sample rate control */ \ 0x0001 /* 9 DSK6713_AIC23_DIGACT Digital interface activation */ \ }; /* * main() - Main code routine, initializes BSL and generates tone */ void main() { DSK6713_AIC23_CodecHandle hCodec; intl_input, r_input, l_output, r_output; /* Initialize the board support library, must be called first */ DSK6713_init(); /* Start the codec */ hCodec = DSK6713_AIC23_openCodec(0, &config); DSK6713_AIC23_setFreq(hCodec, 3); while(1) { /* Read a sample to the left channel */ while (!DSK6713_AIC23_read(hCodec, &l_input)); /* Read a sample to the right channel */ while (!DSK6713_AIC23_read(hCodec, &r_input)); l_output=IIR_FILTER(&filter_Coeff ,l_input); r_output=l_output; /* Send a sample to the left channel */ while (!DSK6713_AIC23_write(hCodec, l_output)); /* Send a sample to the right channel */ while (!DSK6713_AIC23_write(hCodec, r_output)); } /* Close the codec */ DSK6713_AIC23_closeCodec(hCodec); } signedint IIR_FILTER(const signed int * h, signed int x1) { static signed int x[6] = { 0, 0, 0, 0, 0, 0 }; /* x(n), x(n-1), x(n- 2). Must be static */ static signed int y[6] = { 0, 0, 0, 0, 0, 0 }; /* y(n), y(n-1), y(n- 2). Must be static */ int temp=0; temp = (short int)x1; /* Copy input to temp */ 30 2MDC5 Modeling& Simulation Lab x[0] = (signed int) temp; /* Copy input to x[stages][0] */ temp = ( (int)h[0] * x[0]) ; /* B0 * x(n) */ temp += ( (int)h[1] * x[1]); /* B1/2 * x(n-1) */ temp += ( (int)h[1] * x[1]); /* B1/2 * x(n-1) */ temp += ( (int)h[2] * x[2]); /* B2 * x(n-2) */ temp -= ( (int)h[4] * y[1]); /* A1/2 * y(n-1) */ temp -= ( (int)h[4] * y[1]); /* A1/2 * y(n-1) */ temp -= ( (int)h[5] * y[2]); /* A2 * y(n-2) */ /* Divide temp by coefficients[A0] */ temp>>= 15; if ( temp > 32767 ) { temp = 32767; } else if ( temp < -32767) { temp = -32767; } y[0] = temp ; /* Shuffle values along one place for next time */ y[2] = y[1]; /* y(n-2) = y(n-1) */ y[1] = y[0]; /* y(n-1) = y(n) */ x[2] = x[1]; /* x(n-2) = x(n-1) */ x[1] = x[0]; /* x(n-1) = x(n) */ /* temp is used as input next time through */ return (temp<<2); } INPUT OUTPUT 31 2MDC5 Modeling& Simulation Lab Experiment No. # 07 AIM: - To design and implement a low pass FIR filter using windowing technique. APPARATUS: - TMS320C6713 DSK. THEORY:- The total or the average power in a signal is often not of as great an interest. We are most often interested in the PSD or the Power Spectrum. We often want to see is how the input power has been redistributed by the channel and in this frequency-based redistribution of power is where most of the interesting information lies. The total area under the Power Spectrum or PSD is equal to the total avg. power of the signal. The PSD is an even function of frequency or in other words To compute PSD: The value of the auto-correlation function at zero-time equals the total power in the signal. To compute PSD We compute the auto-correlation of the signal and then take its FFT. The auto-correlation function and PSD are a Fourier transform pair. (Another estimation method called “period gram” uses sampled FFT to compute the PSD.) E.g.: For a process x(n) correlation is defined as: R( ) E{x(n) x(n )} N 1 lim N N x ( n) x ( n ) n 1 Power Spectral Density is a Fourier transform of the auto correlation. N 1 S ( ) FT ( R ( )) lim N N 1 ˆ R( )e j 1 R ( ) FT 1 ( S ( )) S ( )e d j 2 ALGORITHM TO IMPLEMENT PSD: Step 1 - Select no. of points for FFT(Eg: 64) Step 2 – Generate a sine wave of frequency ‘f ‘ (eg: 10 Hz with a sampling rate = No. of Points of FFT(eg. 64)) using math library function. Step 3 - Compute the Auto Correlation of Sine wave Step 4 - Take output of auto correlation, apply FFT algorithm . Step 5 - Use Graph option to view the PSD. Step 6 - Repeat Step-1 to 5 for different no. of points & frequencies. 32 2MDC5 Modeling& Simulation Lab ‘C’ Program to Implement PSD: PSD.c: #include <math.h> #define PTS 128 //# of points for FFT #define PI 3.14159265358979 typedefstruct {float real,imag;} COMPLEX; voidFFT(COMPLEX *Y, int n); //FFT prototype floatiobuffer[PTS]; //as input and output buffer float x1[PTS],x[PTS]; //intermediate buffer short i; //general purpose index variable shortbuffercount = 0; //number of new samples in iobuffer short flag = 0; //set to 1 by ISR when iobuffer full float y[128]; COMPLEX w[PTS]; //twiddle constants stored in w COMPLEX samples[PTS]; //primary working buffer main() { floatj,sum=0.0 ; intn,k,i,a; for (i = 0 ; i<PTS ; i++) // set up twiddle constants in w { w[i].real = cos(2*PI*i/(PTS*2.0)); /*Re component of twiddle constants*/ w[i].imag =-sin(2*PI*i/(PTS*2.0)); /*Im component of twiddle constants*/ } /****************Input Signal X(n) *************************/ for(i=0,j=0;i<PTS;i++) { x[i] = sin(2*PI*5*i/PTS); // Signal x(Fs)=sin(2*pi*f*i/Fs); samples[i].real=0.0; samples[i].imag=0.0; } /********************Auto Correlation of X(n)=R(t) ***********/ for(n=0;n<PTS;n++) { sum=0; for(k=0;k<PTS-n;k++) { 33 2MDC5 Modeling& Simulation Lab sum=sum+(x[k]*x[n+k]); // Auto Correlation R(t) } iobuffer[n] = sum; } /********************** FFT of R(t) ***********************/ for (i = 0 ; i < PTS ; i++) //swap buffers { samples[i].real=iobuffer[i]; //buffer with new data } for (i = 0 ; i < PTS ; i++) samples[i].imag = 0.0; //imag components = 0 FFT(samples,PTS); //call function FFT.c /******************** PSD ********************/ for (i = 0 ; i < PTS ; i++) //compute magnitude { x1[i] = sqrt(samples[i].real*samples[i].real + samples[i].imag*samples[i].imag); } } //end of main FFT.c: #define PTS 128 //# of points for FFT typedefstruct {float real,imag;} COMPLEX; extern COMPLEX w[PTS]; //twiddle constants stored in w void FFT(COMPLEX *Y, int N) //input sample array, # of points { COMPLEX temp1,temp2; //temporary storage variables inti,j,k; //loop counter variables intupper_leg, lower_leg; //indexof upper/lower butterfly leg intleg_diff; //difference between upper/lower leg intnum_stages = 0; //number of FFT stages (iterations) int index, step; //index/step through twiddle constant i = 1; //log(base2) of N points= # of stages do { num_stages +=1; 34 2MDC5 Modeling& Simulation Lab i = i*2; }while (i!=N); leg_diff = N/2; //difference between upper&lower legs step = (PTS*2)/N; //step between values in twiddle.h// 512 for (i = 0;i <num_stages; i++) //for N-point FFT { index = 0; for (j = 0; j <leg_diff; j++) { for (upper_leg = j; upper_leg< N; upper_leg += (2*leg_diff)) { lower_leg = upper_leg+leg_diff; temp1.real = (Y[upper_leg]).real + (Y[lower_leg]).real; temp1.imag = (Y[upper_leg]).imag + (Y[lower_leg]).imag; temp2.real = (Y[upper_leg]).real - (Y[lower_leg]).real; temp2.imag = (Y[upper_leg]).imag - (Y[lower_leg]).imag; (Y[lower_leg]).real = temp2.real*(w[index]).real -temp2.imag*(w[index]).imag; (Y[lower_leg]).imag = temp2.real*(w[index]).imag +temp2.imag*(w[index]).real; (Y[upper_leg]).real = temp1.real; (Y[upper_leg]).imag = temp1.imag; } index += step; } leg_diff = leg_diff/2; step *= 2; } j = 0; for (i = 1; i < (N-1); i++) //bit reversal for resequencing data { k = N/2; while (k <= j) { j = j - k; k = k/2; } j = j + k; if (i<j) { temp1.real = (Y[j]).real; temp1.imag = (Y[j]).imag; (Y[j]).real = (Y[i]).real; (Y[j]).imag = (Y[i]).imag; (Y[i]).real = temp1.real; (Y[i]).imag = temp1.imag; } } return; } 35 2MDC5 Modeling& Simulation Lab OUT PUT: 36 2MDC5 Modeling& Simulation Lab Experiment No. # 08 AIM:- To compute The Discrete Cosine Transform EQUIPMENT USED:-TMS320C6713 DSK THEORY:- The discrete cosine transform (DCT) helps separate the image into parts (or spectral sub-bands) of differing importance (with respect to the image's visual quality). The DCT is similar to the discrete Fourier transform: it transforms a signal or image from the spatial domain to the frequency domain. With an input image, A, the coefficients for the output "image," B, are: The input image is N2 pixels wide by N1 pixels high; A(i,j) is the intensity of the pixel in row i and column j; B(k1,k2) is the DCT coefficient in row k1 and column k2 of the DCT matrix. All DCT multiplications are real. This lowers the number of required multiplications, as compared to the discrete Fourier transform. The DCT input is an 8 by 8 array of integers. This array contains each pixel's gray scale level; 8 bit pixels have levels from 0 to 255. The output array of DCT coefficients contains integers; these can range from -1024 to 1023. For most images, much of the signal energy lies at low frequencies; these appear in the upper left corner of the DCT. The lower right values represent higher frequencies, and are often small - small enough to be neglected with little visible distortion. IMPLEMENTATION OF DCT DCT-based codecs use a two-dimensional version of the transform. The 2-D DCT and its inverse (IDCT) of an N x N block are shown below: 2-D DCT: 2 N 1 N 1 (2 x 1)u (2 y 1)v F (u , v) C (u )C (v) f ( x, y ) cos[ ] cos[ ] N y 0 x 0 2N 2N 2-D IDCT: 2 N 1 N 1 (2 x 1)u (2 y 1)v f ( x, y ) N C (u)C (v) F (u, v) cos[ v 0 u 0 2N ] cos[ 2N ] One of the properties of the 2-D DCT is that it is separable meaning that it can be separated into a pair of 1-D DCTs. To obtain the 2-D DCT of a block a 1-D DCT is first performed on the rows of the block then a 1-D DCT is performed on the columns of the resulting block. The same applies to the IDCT. 37 2MDC5 Modeling& Simulation Lab This process is illustrated below. Precalculate the DCT coefficients and scale them Note that the values in the decimal format does not include the factor [Sqrt(2/n)=>sqrt(2/8)=>1/2]. The reason for this is that dividing the coefficients by 2 before converting to Q12 may result in some loss in precision. More precision can be obtained by ignoring this division and then multiplying by 211 (instead of 212 ) to convert to Q12. The reason for using Q12 instead of Q15 (as one would expect) is as follows. Referring to Equation [3], we notice that the DCT calculation involves a summation of N terms. Looking 38 2MDC5 Modeling& Simulation Lab at the DCT coefficients in Figure 1, we observe that the terms entering in the summation may be close to 1. Thus, such summation may cause overflows. To avoid this, each term must be scaled down by 1/N. For N=8, this can be achieved by working in Q12 format instead of Q15 format. PROGRAM:- Main.c: #include <stdio.h> #include <stdlib.h> #include "dct.h" #include "scenary.h" /* Header file containing input image as a 1D array */ #pragma DATA_SECTION (image_in,"ext_sdram") #pragma DATA_SECTION (image_out,"ext_sdram") /* 1D array to hold output image */ unsigned char image_out[IMAGE_SIZE]; /* 1D array to hold the current block */ short block[BLOCK_SIZE]; /* Q12 DCT coefficients (actual coefficient x 2^12 ) */ const short coe[8][8]= { 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 5681, 4816, 3218, 1130, -1130, -3218, -4816, -5681, 5352, 2217, -2217, -5352, -5352, -2217, 2217, 5352, 4816, -1130, -5681, -3218, 3218, 5681, 1130, -4816, 4096, -4096, -4096, 4096, 4096, -4096, -4096, 4096, 3218, -5681, 1130, 4816, -4816, -1130, 5681, -3218, 2217, -5352, 5352, -2217, -2217, 5352, -5352, 2217, 1130, -3218, 4816, -5681, 5681, -4816, 3218, -1130 }; extern void dct(void); extern void idct(void); void main() { inti,x; /* Perform block by block processing */ for(i=0;i<IMAGE_SIZE;i+=BLOCK_SIZE) { /* Get the block from the input image */ for(x=0;x<BLOCK_SIZE;++x) { block[x] = (short) image_in[i+x]; } 39 2MDC5 Modeling& Simulation Lab /* Perform DCT on this block */ dct(); /* Perform IDCT on this block */ idct(); /* Store block to output image */ for(x=0;x<BLOCK_SIZE;++x) { if(block[x]<0) { image_out[i+x]=(unsigned char) (-block[x]); /* Quick fix for errors occuring due to negative a values occuring after IDCT! */ } else { image_out[i+x]=(unsigned char) block[x]; } } } //for (;;); /* Wait */ } dct.c: /*********************************************************************/ /* dct.c Function to perform a 8 point 2D DCT */ /* DCT is performed using direct matrix multiplication */ /*********************************************************************/ #include "dct.h" extern unsigned char image_in[IMAGE_SIZE]; extern unsigned char image_out[IMAGE_SIZE]; extern short block[BLOCK_SIZE]; externconst short coe[8][8]; voiddct(void) { inti,j,x,y; int value[8]; /* Perform 1D DCT on the columns */ for(j=0;j<8;j++) { for(y=0;y<8;++y) 40 2MDC5 Modeling& Simulation Lab { value[y]=0; for(x=0;x<8;++x) { value[y] += (int)(coe[y][x]*block[j+(x*8)]); } } for(y=0;y<8;++y) { block[j+(y*8)] = (short)(value[y]>>12); } } /* Perform 1D DCT on the resulting rows */ for(i=0;i<64;i+=8) { for(y=0;y<8;++y) { value[y] = 0; for(x=0;x<8;++x) { value[y] += (int)(coe[y][x]*block[i+x]); } } for(y=0;y<8;++y) { block[i+y] = (short)(value[y]>>15); } } } idct.c: /*********************************************************************/ /* idct.c performs a 8 point 2D Inverse DCT function */ /*********************************************************************/ #include "dct.h" extern unsigned char image_in[IMAGE_SIZE]; extern unsigned char image_out[IMAGE_SIZE]; extern short block[BLOCK_SIZE]; externconst short coe[8][8]; voididct(void) 41 2MDC5 Modeling& Simulation Lab { inti,j,x,y; int value[8]; /* Perform 1D IDCT on the columns */ for(j=0;j<8;j++) { for(y=0;y<8;++y) { value[y] = 0; for(x=0;x<8;++x) { value[y] += (int)(coe[x][y]*block[j+(x*8)]); } } for(y=0;y<8;++y) { block[j+(y*8)] = (short)(value[y]>>12); } } /* Perform 1D IDCT on the resulting rows */ for(i=0;i<64;i+=8) { for(y=0;y<8;++y) { value[y] = 0; for(x=0;x<8;++x) { value[y] += (int)(coe[x][y]*block[i+x]); } } for(y=0;y<8;++y) { block[i+y] = (short)(value[y]>>15); } } } MY_LNK_CMD.cmd: -l imagecfg.cmd SECTIONS { 42 2MDC5 Modeling& Simulation Lab mydata > SDRAM mycode> SDRAM ext_sdram> SDRAM } image_in: image_out: 43