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					ELEN 468
Advanced Logic Design
Lecture 10
Behavioral Descriptions IV




              ELEN468 Lecture 10   1
Finite State Machines
                    Mealy Machine
input                                              output
        Next state and output
        Combinational logic                 Register

                                    clock



                    Moore Machine
input
            Next state                                   Output          output
                                  Register
        Combinational logic                        Combinational logic
                          clock



                              ELEN468 Lecture 10                           2
Explicit Finite State Machines 1
 module FSM_style1 ( … );
   input …;
   output …;
   parameter size = …;
   reg [size-1:0] state;
   wire [size-1:0] next_state; // different from textbook
                              // which is wrong

    assign outputs = …; // function of state and inputs
    assign next_state = …; // function of state and inputs

   always @ ( negedge reset or posedge clk )
     if ( reset == 1`b0 ) state = start_state;
     else state <= next_state;
 endmodule

                            ELEN468 Lecture 10               3
Explicit Finite State Machines 2
 module FSM_style2 ( … );
   input …;
   output …;
   parameter size = …;
   reg [size-1:0] state, next_state;

    assign outputs = …; // function of state and inputs

    always @ ( state or inputs )
      begin
         // decode for next_state with case or if statement
      end

   always @ ( negedge reset or posedge clk )
     if ( reset == 1`b0 ) state = start_state;
     else state <= next_state;
 endmodule

                               ELEN468 Lecture 10             4
Explicit Finite State Machines 3
 module FSM_style3 ( … );
   input …;
   output …;
   parameter size = …;
   reg [size-1:0] state, next_state;

   always @ ( state or inputs )
     begin
          // decode for next_state with case or if statement
     end
   always @ ( negedge reset or posedge clk )
     if ( reset == 1`b0 ) state = start_state;
     else begin
          state <= next_state;
          outputs <= some_value ( inputs, next_state );
       end
 endmodule

                               ELEN468 Lecture 10              5
Summary of Explicit FSM
  States are defined explicitly
  FSM_style1
     Minimum behavioral description
  FSM_style2
     Use behavioral to define next state, easier
      to use
  FSM_style3
     Output synchronized with clock

                   ELEN468 Lecture 10           6
FSM Example: Speed Machine
                         a = 1, b = 0

                                                                 a: accelerator
                low                     stopped         b=1
                           b=1                                   b: brake
a = 1, b = 0




                         accelerator
                  b=1




                              brake                                         speed
                               clock


                           b=1
               medium                    high           a = 1, b = 0


                        a = 1, b = 0

                                   ELEN468 Lecture 10                           7
Verilog Code for Speed Machine
// Explicit FSM style                            always @ ( state or accelerator or brake )
module speed_machine ( clock,                      if ( brake == 1`b1 )
     accelerator, brake, speed );                    case ( state )
                                                         stopped: next_state <= stopped;
    input clock, accelerator, brake;                     s_low: next_state <= stopped;
    output [1:0]      speed;                             s_medium: next_state <= s_low;
                                                         s_high: next_state <= s_medium;
    reg    [1:0]      state, next_state;
                                                         default: next_state <= stopped;
                                                     endcase
    parameter    stopped = 2`b00;                  else if ( accelerator == 1`b1 )
    parameter    s_slow = 2`b01;                     case ( state )
    parameter    s_medium = 2`b10;                       stopped: next_state <= s_low;
    parameter    s_high = 2`b11;                         s_low: next_state <= s_medium;
                                                         s_medium: next_state <= s_high;
    assign speed = state;                                s_high: next_state <= s_high;
                                                         default: next_state <= stopped;
    always @ ( posedge clock )                       endcase
      state <= next_state;                         else next_state <= state;
                                              endmodule

                                     ELEN468 Lecture 10                                   8
Implicit Finite State Machine
module speed_machine2 ( clock,              always @ ( posedge clock )
   accelerator, brake, speed );               if ( brake == 1`b1 )
                                                  case ( speed )
  input clock, accelerator, brake;                   `stopped: speed <= `stopped;
  output [1:0] speed;                                `low: speed <= `stopped;
  reg [1:0] speed;                                   `medium: speed <= `low;
                                                     `high: speed <= `medium;
  `define stopped 2`b00                              default: speed <= `stopped;
  `define low 2`b01                               endcase
  `define medium 2`b10                        else if ( accelerator == 1`b1 )
  `define high 2`b11                              case ( speed )
                                                     `stopped: speed <= `low;
                                                     `low: speed <= `medium;
                                                     `medium: speed <= `high;
                                                     `high: speed <= `high;
                                                     default: speed <= `stopped;
                                                  endcase
                                          endmodule

                                     ELEN468 Lecture 10                             9
Another Implicit FSM Example
module speed_machine3 ( clock,              always @ ( posedge clock )
   accelerator, brake, speed );               case ( speed )
                                                `stopped: if ( brake == 1`b1 )
  input clock, accelerator, brake;                              speed <= `stopped;
  output [1:0] speed;                                 else if ( accelerator == 1`b1 )
  reg [1:0] speed;                                              speed <= `low;
                                                `low: if ( brake == 1`b1 )
  `define stopped 2`b00                                         speed <= `stopped;
  `define low 2`b01                                   else if ( accelerator == 1`b1 )
  `define medium 2`b10                                          speed <= `medium;
  `define high 2`b11                            `medium: if ( brake == 1`b1 )
                                                                speed <= `low;
                                                      else if ( accelerator == 1`b1 )
                                                                speed <= `high;
                                                `high: if ( brake == 1`b1 )
                                                                speed <= `medium;
                                                default: speed <= `stopped;
                                             endcase
                                          endmodule


                                     ELEN468 Lecture 10                                 10
Handshaking
     Server                                Client

        data_out                  8      data_in

    server_ready                         server_ready

     client_ready                        client_ready




                    ELEN468 Lecture 10                  11
Algorithm State Machine (ASM) Chart
   s_idle / SR = 0                                c_idle / CR = 0
        #                                              #
   s_wait / SR = 1                            c_wait / CR = 1


                     0                                         0
         CR                                             SR
        1 #                                            1 #

  s_serve / SR = 1                            c_client / CR = 1
          #                                                #
  s_done / SR = 0                             c_done / CR = 0

                         #                                          #
   1                                                           0
        CR    0                                    1   SR


                             ELEN468 Lecture 10                         12
Verilog Code for Handshaking
module server ( d_out, s_ready, c_ready );      module client ( d_in, s_ready, c_ready );
  output [3:0] d_out; output s_ready;             input [3:0] d_in; input s_ready;
  input c_ready;                                  output c_ready;
  reg s_ready; reg [3:0] d_out;                   reg c_ready; reg [3:0] data_reg;
  task pause;                                     task pause;
    reg [3:0] delay;                                 reg [3:0] delay;
    begin delay = $random;                           begin delay = $random;
       if ( delay == 0 ) delay = 1;                     if ( delay == 0 ) delay = 1;
       #delay; end                                      #delay; end
  endtask                                         endtask
  always                                          always begin
    forever begin                                    c_ready = 0; pause; c_ready = 1;
       s_ready = 0; pause; s_ready = 1;              forever begin
       wait ( c_ready ) pause;                         wait ( s_ready ) pause;
       d_out = $random; pause;                          data_reg = d_in; pause; c_ready = 0;
       s_ready = 0;                                     wait ( !s_ready ) pause; c_ready = 1;
       wait ( !c_ready ) pause;                      end
     end                                          end
endmodule                                       endmodule


                                    ELEN468 Lecture 10                                 13
Polling Circuit
          Each client cannot be served
          for 2 consecutive cycles

                   client1                                    service
                                        clock             3   request
 Server            client2                      Polling
                                        reset   circuit   2
                                                              service
                   client3                                    code
                  Highest
                  priority




                         ELEN468 Lecture 10                        14
State Transition Graph for Polling Circuit
                                             100

                                         Client3
      Service request
                                             11
                                                            -01
                 -1-                   1--
                             1--                   000    1--

   010                       000                            000             001
         Client2                          None                    Client1
            10               01-             00           001       01
                                                    000   0-1
 Service code          01-



                                   ELEN468 Lecture 10                        15
Verilog Code for Polling Circuit
module polling ( s_request, s_code, clk, rst );      task poll_them;
 `define client1 2`b01                                 input [1:0] present_client;
 `define client2 2`b10                                 input [3:1] s_request;
 `define client3 2`b11                                 output [1:0] next_client;
 `define none 2`b00                                    reg [1:0] contender; integer N;
 input [3:1] s_request;                                begin: poll
 input clk, rst; output [1:0] s_code;                     contender = `none;
 reg [1:0] next_client, present_client;                   next_client = `none;
 always @ ( posedge clk or posedge rst )                  for ( N = 3; N >= 1; N = N – 1 )
   begin if ( rst )                                           begin: decision
      present_client = `none;                                    if ( s_request[N] ) begin
      else present_client = next_client;                            if ( present_client == N )
   end                                                                  contender = present_client;
 assign s_code[1:0] = present_client;                                else begin next_client = N;
 always @ ( present_client or s_request )                               disable poll; end
   begin                                                             end end
      poll_them ( present_client, s_request,              if (( next_client == `none ) &&
                   next_client );                             ( contender ))
   end                                                        next_client = contender; end
                                                     endtask endmodule



                                      ELEN468 Lecture 10                                    16
Test Bench for Polling Circuit
moduel test_polling;                                initial
 reg [3:1] s_request; reg clk, rst;                    begin
 wire [1:0] s_code;                                       #20 s_request = 3`b100;
 wire sreq3 = M1.s_request[3];                            #20 s_request = 3`b010;
 wire sreq2 = M1.s_request[2];                            #20 s_request = 3`b001;
 wire sreq1 = M1.s_request[1];                            #20 s_request = 3`b100;
 wire [1:0] NC = M1.next_client;                          #40 s_request = 3`b010;
 wire [1:0] PC = M1.present_client;                       #40 s_request = 3`b001;
 wire [3:1] s_req = s_request;                         end
 wire [1:0] s_cd = s_code;                          initial
 polling M1 ( s_request, s_code, clk, rst );           begin
 initial begin                                            #180 s_request = 3`b111;
       clk = 0; forever #10 clk = ~clk;                   #60 s_request = 3`b101;
    end                                                   #60 s_request = 3`b011;
 initial #400 finish;                                     #60 s_request = 3`b111;
 initial begin                                            #20 rst = 1;
       rst = 1`bx;                                     end
       #25 rst = 1; #75 rst = 0;                  endmodule
    end


                                      ELEN468 Lecture 10                             17
Exercise 2
  ELEN468 Lecture 10   18
Find Error
module something_wrong ( y_out, x1, x2 );
  output y_out;
  input x1, x2;

  `define delay1 3;    // No “;”
  `define delay2 4;
  `define delay3 5;

  nand #(delay1, delay2, delay3) ( y_out, x1, x2 );
   // No turnoff delay for non-3-state gate
   // Remove “delay3”, or replace “,” with “:”
endmodule


                        ELEN468 Lecture 10            19
Timing Models
  Determine time values in simulation
     `timescale 10ns/1ps 2.447 24.470ns
     `timescale 1ns/100ps 2.447 2.4ns
  What is the typical falling delay from a1
  to y2?
  (a1,a2 *> y1, y2) = (7:8:9, 6:10:12);
  10


                ELEN468 Lecture 10         20
Correct Error
module flop ( clock, data, q, qbar, reset );
  input clock, data, reset;
  output q, qbar;
  reg q;

   assign qbar = ~q;

  // This cannot model flip-flop properly
   // when reset rises and clock == 1
  always @ ( posedge clock or reset )
      begin
        if ( reset == 0 ) q = 0;
        else if ( clock == 1 ) q = data;
      end
endmodule


                            ELEN468 Lecture 10   21
What will happen?
module A ( … );
  …
  initial
     clock = 0;

  // Nothing will happen
  always @ ( clock )
     clock = ~clock;

  …
endmodule



                           ELEN468 Lecture 10   22

				
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