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Three stage Nested Miller
Low-Voltage Amplifier
Group1
Parmoon Seddighrad
Carlos Tokunaga
Eric Sun
Motivation for Multistage Amp.
Reduction in Supply Voltage
High gain, large bandwidth operational amplifier
Cascoding will not work with low power supply
Nested Miller Compensation (NMC) is used to
increase the stability
12/10/03 EECS 413 - Three stage Nested Miller Low-Voltage Amplifier
Specification
Power Supply 1.5 V (+/- 5%)
Gain 75 dB
Phase Margin 65 degree
Temperature 27-85 C
Load Capacitance 2 pf
Band Width 100 MHz
12/10/03 EECS 413 - Three stage Nested Miller Low-Voltage Amplifier
Design Flow
Evaluation of
Circuit Topology
Ideal Op-Amp
Simulation
How many stages are needed?
Transistor Level
How much gain is need for each
Simulation
stage?
NO Meet The
Specification?
Structure Consideration
YES
Zero resistor compensation
Layout ( suffer from temperature variation)
NO
Meet The
Feedforward-path
Post Simulation
Specification?
(sensitive to Vdd-variation because of multipath)
YES
Nested Miller compensation (NMC)
Done!
12/10/03 EECS 413 - Three stage Nested Miller Low-Voltage Amplifier
Three-Stage Op-amp
`
`
f f
12/10/03 EECS 413 - Three stage Nested Miller Low-Voltage Amplifier
Advantages of our architecture
Easier design
(1 diff. amp and 2 cs amp)
More degrees of freedom for
compensation
Avoid to use cascode
Low voltage is possible
12/10/03 EECS 413 - Three stage Nested Miller Low-Voltage Amplifier
Nominal Results
Vdd Gain BW PM
(V ) (dB ) (MHz ) Degree
1.5 92 113 70
12/10/03 EECS 413 - Three stage Nested Miller Low-Voltage Amplifier
VDD Variations
Vdd Gain BW PM
(V ) (dB ) (MHz ) Degree
1.485 79.84 110 68
1.492 91.15 112 66
1.5 92.21 113 70
1.508 85.99 115.5 69
1.515 76.49 119 69
12/10/03 EECS 413 - Three stage Nested Miller Low-Voltage Amplifier
Common Voltage Variations
VCM Gain BW PM
(mV ) (dB ) (MHz ) Degree
340 78.47 116.6 67.3
350 86 114.5 70
360 92.21 113 70
370 91.98 113.2 70
380 94.39 112.5 68.9
12/10/03 EECS 413 - Three stage Nested Miller Low-Voltage Amplifier
Temperature Variations
Temp. Gain BW PM
( 0C ) (dB ) (MHz ) Degree
27 92.21 113.3 70
41 91.52 110.7 69
56 90.47 109.6 68
70 89.25 107.8 67
85 87.91 105.7 67
12/10/03 EECS 413 - Three stage Nested Miller Low-Voltage Amplifier
Layout
Bias ckt 3rd stage
1st 2nd
stage stage Miller Cap.
Miller Cap. 3rd Miller
stage Cap.
12/10/03 EECS 413 - Three stage Nested Miller Low-Voltage Amplifier
Post Simulation – Vcm Variations
VCM Gain BW PM
(mV ) (dB ) (MHz ) Degree
340 91.75 106.8 72
350 89.00 106.8 72
360 79.92 105.2 69
370 71.25 101.7 66
380 67.71 98.3 62
12/10/03 EECS 413 - Three stage Nested Miller Low-Voltage Amplifier
Post Simulation – Vcm Variations
12/10/03 EECS 413 - Three stage Nested Miller Low-Voltage Amplifier
Post Simulation - VDD Variations
Vcm = 0.36V Vcm = 0.34V
Vdd Gain BW PM Vdd Gain BW PM
(V ) (dB ) (MHz ) Degree (V ) (dB ) (MHz ) Degree
1.485 66.39 97.1 61.5 1.485 74.84 102.2 66
1.492 70.21 100.1 65 1.492 81.89 106.3 68
1.5 79.92 100.5 69 1.5 88.33 107.7 69
1.508 90.89 100.7 72 1.508 89.49 109.3 69
1.515 92.55 100.7 72 1.515 91.73 109.3 70
12/10/03 EECS 413 - Three stage Nested Miller Low-Voltage Amplifier
Post Simulation – temp. Variations
Vcm = 0.36V Vcm = 0.34V
Temp. Gain BW PM Temp. Gain BW PM
( 0C ) (dB ) (MHz ) Degree ( 0C ) (dB ) (MHz ) Degree
27 79.9 100.5 70 27 91.75 106.6 72
41 75.82 110.2 69 41 90.23 104.5 73
56 73.50 98.93 66 56 88.59 109.6 71
70 71.22 96.22 65.1 70 86.84 102.2 69
85 69.74 94.00 64 85 85.01 97.35 68
12/10/03 EECS 413 - Three stage Nested Miller Low-Voltage Amplifier
Performance Summary
Process(0.25um) Post-Sim
Power Supply 1.5 V (+/- 5%) 1.5 V (+/- 1%)
Gain 75 dB > 75dB
Phase Margin 65 degree ~ 68 degree
Temperature 27-85 C 27-85 C
Load Capacitance 2 pf 2pF
Band Width 100 MHz 100MHz
12/10/03 EECS 413 - Three stage Nested Miller Low-Voltage Amplifier
Plot of comparing our op-amp with
the state of art literature
Pub Tech BW Gain PM Load Vdd Power
Ours 0.25u 92dB/113MHz 70 2pF 1.5V 2m
2 -4 2u 100dB/1MHz 58 +/-1V 1.4m
3 -3 1.2u 96dB/1.1MHz 56.7 20pF 2V .26m
4-4 1.2u 100dB/1.5MHz 70 16pF 1.5V .5m
5–3 0.8u 100dB/5.9kHz 43 100pF +/-1V .4m
6–2 0.6u 102dB/47MHz 76 40pF 3V 6.9m
7-3 0.8u 100dB/382kHz 70 100pF 2V .3m
8 0.8u 100dB/4.5MHz 65 120pF 2V .4m
12/10/03 EECS 413 - Three stage Nested Miller Low-Voltage Amplifier
Conclusions
Immunity to temperature variation
Input common-mode voltage range is
small
Sensitive to Vdd variation
self-biasing is needed
12/10/03 EECS 413 - Three stage Nested Miller Low-Voltage Amplifier
References
R. Castello, “A CMOS low-distortion fully differential power amplifier with double
nested miller compensation”, IEEE Journal of Solid-state circuits, 1993, v.28 n.3
E. Sanchez-Sinencio, “Multistage amplifier topologies with nested Gm-C
Compensation”, IEEE Journal of Solid-State Circuits, 1997, v.32 n. 12, pp. 2000-2011
M.C. Scheneider, “Sound design of low power nested transconductance-capacitance
compensation amplifiers”, Electronics Letters, 1999, v.35 n.12, pp. 956-958
E. Sancehz-Sinencio, “A low Voltage fully differential nested Gm capacitance
compensation amplifier: Analysis and design”, 1999
W.H. Ki, “Optimum nested miller compensation for low-voltage low-power cmos
amplifier design”, 1999
D. J. Allstot, “A multistage amplifier technique with embedded frequency
compensation”, IEEE Journal of Solid-state circuits, 1999, v.34 n.3
S. Pennisi, “Design guidelines for optimized nested miller compensation”, 2000
P.K.T. Mok, “Active-feddback frequency-compensation technique for low-power
multistage amplifiers”, IEEE Journal of Solid-state circuits, 2003, v.38 n.3
12/10/03 EECS 413 - Three stage Nested Miller Low-Voltage Amplifier
