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Functional Synthesis and Verification
      of Finite State Machines

      Alan Mishchenko, PSU
     Anatoly Chebotarev, GIC
      Marek Perkowski, PSU
              Algorithms
•   FSM specification using time constraints
•   Internal data representation using BDDs
•   Minimum-state FSM synthesis by construction
•   Determinization and specification completion
•   Verification using R-resolution (new method)
•   FSM decomposition (forthcoming)
Practical Applications
• Provably correct design of real-time
  (reactive, hybrid) systems
• Protocol design and verification
• Synthesis of minimum state
  (non)deterministic FSMs
• FSM design for future technologies
  (“canonical machines”)
      SYNTHA
 Logic Synthesis and Verification
    of Finite State Machines

    Alan Mishchenko, PSU
     Andrey Mishchenko,
Glushkov Institute, Kiev, Ukraine
             Algorithms
•   Table method for FSM specification
•   Transparent logic synthesis algorithms
•   Economic implementation of next-state logic
•   Two-level boolean optimization (Espresso)
•   VHDL output
•   Synthesis for testability (forthcoming)
•   Technology mapping (forthcoming)
 Practical Applications
• Human-guided FSM specification and
  design of efficient controller
• Logic Synthesis of economical FSMs
• Building FSMs from universal blocks such
  as counters, shifters, EXOR modifiers
• Using various encodings and flip-flop types
• Adaptations for PLA, FPGA, ASIC
• Producing VHDL output
         TRACE
Glimpses into the Inner Structure of
   “Cyclic” Boolean Functions
     and Autonomous FSMs
    Alan Mishchenko, PSU
     Andrey Mishchenko,
Glushkov Institute, Kiev, Ukraine
           Algorithms
• New concept of “cyclic” boolean functions
• Finding “traces” of “cyclic” boolean
  functions for different types of flip-flops
• Properties of known and random functions
• Multi-zoom visualization using MFC
 Practical Applications
• Research in boolean functions
• Synthesis of economical control units using
  embedded autonomous FSMs
• Design of FSMs using AND/EXOR circuits
  optimized for speed, area, and testability
• Case Study: Efficient reversible counters
         MVGUD
  Decomposition of Multi-Valued
Multi-Output Functions and Relations

      Marek Perkowski, PSU
       Stan Grygiel, PSU
          Algorithms
• Decomposition strategy selection
• Variable partitioning (new algorithms)
• New Data Structure for weakly-specified
  functions and relations (LR-partitions)
• Column multiplicity (graph coloring)
• Decomposition evaluation using DFC
• Iterative processing of decompositions
• Verification of final results
    Practical Applications
•   Boolean and Multi-Valued Logic Synthesis
•   Finite State Machine Decomposition
•   Data Mining and Machine Learning
•   Digital Image Processing
•   Artificial Intelligence
•   Evolutionary Algorithms
                  Relation                        Function

                                                                              Relation



.type mv                          0100-11--   1       .type mv        . .type mv      . .type mv
.i 9                              1000-11--   1       .i 3            .i 3            .i 3
.o 1                              00-0111--   1       .o 1            .o 1            .o 1
.ilb i0 i1 i2 i3 i4 i5 i6 i7 i8   01-0101--   1       .ilb i0 i1 i2   .ilb i3 i4 i5   .ilb i3 i4 i5
.ob o0                            110-010--   1       .ob s2.0        .ob s2.1        .ob s2.1
.imv 2 2 2 2 2 2 2 2 2            101-100--   1       .imv 2 2 2      .imv 2 2 2      .imv 2 2 2
.omv 2                            01-1100--   1       .omv 4          .omv 4          .omv 4
.p 156                            0101-0-1-   1       .p 8            .p 8            .p 8
00011-1-- 1                       -01100-1-   1       010 1           010 1           010 1
01100-1-- 1                       00--0111-   1       011 0           110 0           110 0
10100-1-- 1                       --001011-   1       110 0           111 2           111 2
0100-11-- 1                       01--0011-   1       111 2           100 1           100 1
1000-11-- 1                       .end                100 1           101 0           101 0
                                                      101 0           .end            .end
                                                      .end

				
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posted:3/22/2012
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