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Physical Layer Driven Protocol and Algorithm Design for Energy

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					Fault-Tolerant design of RF front-end circuits

              P.R. Mukund, Ph.D.
     Gleason Professor of Electrical Engineering
   Director, RF/Analog/Mixed-signal Lab (RAMLAB)




         Rochester Institute of Technology
              Rochester, NY 14623
                                        Funding



     Industry Liaisons

                      Henning Braunisch



                       Hosam Haggag
                                                  This work was
                                                  funded by the
                                                  Semiconductor
                                                  Research Corporation
                       Ronald McBean
                       (Motorola)




Fault-Tolerant Design of RF Front end Circuitry
                                      Motivation

                                                                           RF Modules               Horizontal Floor
    SoC, SiP implementations                      Passives
                                                                                                       Planning

                                                                 Digital
    High levels of integration                                  Modules

                                                                                        RF Design
          Complex interaction between RF,
                                                                                   Digital Logic
           analog, & digital domains
                                                                              MEMS
    Heightened sensitivity to                                CHIPCARRIER

     package parasitics, wide
     tolerances


                                             Mutual-coupling, electro-magnetic
                                              coupling, stray inductances
                                             Gap between models and silicon
                                             Several design iterations, higher costs
                                              and lower yield for RFICs


Fault-Tolerant Design of RF Front end Circuitry
                     Need for Fault-tolerance in RF circuits

              Probes
                                                 Complex behavioral, modeling and
                                                  fabrication problems
                                                     More faults and higher variations
Si Die
                                 RF Testing
         RF Design                               Poor, unpredictable Q-factors

   Testing is expensive (ATE)
     Veryact of probing affects performance
     Access to RF core difficult

 Yield of RFICs 10%-12% less than
digital ASICs

                        Post fabrication processing is needed
                        Analog/Digital techniques not relevant for RF circuits
                        Novel fault-tolerance techniques for RF required !

Fault-Tolerant Design of RF Front end Circuitry
                                        Background

   Self-test solutions with high overheads
        Computation, real-estate, DSP, power
   ATE testing very expensive (40% of chip cost)
                      010010101000
                      010101001000
                      111001000011
                                                         Can detect but
                      000010101000
                      010101011111
                                                            not correct
                                                                 faults
                                                                          Limitations
     High Cost $$    Use of DSPs        Time Intensive



    Fault-tolerance                 in digital circuits
         Reconfigurabilityand redundancy
         Huge real-estate and power overheads for RF

    Fault-tolerance     in analog circuits
            No Prior art for fault-tolerant RF design
         Feedback  mechanisms
         Not practical for HF circuits

    Parametric          fault-modeling for analog circuits
Fault-Tolerant Design of RF Front end Circuitry
                                                                                     Summary of Prior Work



                                                                                                                                                                  Digital Pin
                                                                                                                                                                  Placement
                                                                                                               Mixed Signal
                                                                                                                 Analysis



                                                                                                         A/D and
                                                                                                         Op-Amp Analysis



    Design Methodologies
           RF                     Horizontal                                       Passive
          Modules               Floor Planning                                 Characterization
                                                                                                                                                                   Power
Digital                                                                                                                                                          Distribution
Modules
                     RF Design                                                                                       RF
              Digital Logic                                                Inductor
                                Vertical
             MEMS                                                           Library                                                                2D and 3D Analysis for
                              Integration                                                                      Phase Noise Analysis for VCO &
                                                                                                                                                   Power Distribution Analysis
                                                                  40
                                                                                       L1 off chip
                                                                                                               Sideband Analysis for Mixer
                                                 Quality Factor




                                                                  35                   L2 off chip
                                                                                       L1 on chip


  Novel Design
                                                                  30                   L2 on chip




   Techniques
                                                                  25

                                                                  20                                                                 Early Design Software – ‘DREAM’
                                                                  15

                                                                  10                                            Inductor Libraries
                                                                                                                for RF Design
                                                                  5
                                                                                   Frequency(GHz)
                                                                  0
                                                                       0   2   4      6              8



                                                                                                              Inductor Modeling
                                                                                                              and Characterization


                                                                                                                Vertically Integrated Designs
                                                                                                                (Si on Si)
    Fault-Tolerant Design of RF Front end Circuitry
                                                 Prior BIST Architecture




                                                                                  TASKS
                                                                     Development of an accurate and
                                                                     non-intrusive current monitor
                                                                     Fault modeling of 3D Stacked RF
                                                                     circuits
                                                                     Analyzing and quantifying various
                                                                     factors leading to performance
                                                                     degradation
                                                                     Development of current signatures
                                                                     - Mapping circuit performance to
                                                                     supply current.
                                                                     Integrating information into a
                          Proposed BIST Architecture                 BIST architecture



 Dr P.R.Mukund, RF / Analog / Mixed Signal Lab
Fault-Tolerant Design of RF Front end Circuitry
                         Feedback for RF circuits?


         Why feedback will not work
                                                             Very little gain
                                                             available for trade-off


                                                         Stability issues @ GHz:
                                                         Mutual coupling, Ground
           Alternative
                                                         loops, Metal trace
                                                         parasitics


              An approach that                          Transformers, inductors,
              overcomes these                           etc., have wide tolerances
              roadblocks, yet
              retains its usability   √
                                                  Feedback    Re-design of circuit !

Fault-Tolerant Design of RF Front end Circuitry
                                    This work….

   Alternative fault-tolerance methods for RF circuits
        Overcome limitations of traditional feedback
   Emphasis on low overhead, minimally intrusive,
    low-cost solutions
   Robust circuitry/algorithms for error-free
    operation
   Low-frequency/DC post-processing
   No DSP/off-chip processing, ultra-fast




Fault-Tolerant Design of RF Front end Circuitry
             Methodology: ‘Locked loop’ concept

                                          Sense Amplifier       Peak Detector


                        Sense current            Amplify               Down-           Map signal to
        Start with      with minimally           sensed                convert         performance
         nominal           intrusive
                                                 current              signal to           metric
          design           element
                                                                      baseband

                          RF
                       CIRCUIT

                                     Dynamically               Generate           NO
                                                                                         Performan
                                    modify design          baseband/digital              ce metric
                                   parameters in RF        signal to modify                 ok?
                                        circuit                 design
                                                              parameters
                                                                                       YES




                                                            Baseband Signal                 End
                                                            Processing                  Calibration
                                                                                         process


            Specification based correction

Fault-Tolerant Design of RF Front end Circuitry
                        ‘Locked Loop’ approach


                                    Four fold approach


             Sense                   To sense a signal which is indicative of the
                                     performance metric of the circuit


           Quantify                   To process this signal appropriately into a form
                                      which quantitatively describes the metric


       Self-corrective               Use this information to send a signal back to
                                     the circuit where the metric can be re-
            signal
                                     corrected towards the desired value
                                      A mechanism in the circuit which can
         Tapped coil                  adaptively change its performance in real
                                      time based on the above signal.


Fault-Tolerant Design of RF Front end Circuitry
                    Minimally Intrusive Sensing

   S21 & S22 degraded        No effect on S11

                                                  S22 & S21 degraded
                                                   Resistor in return path!




                                                  S22 & S21 unaffected
                                                   S11 degraded
                                                   Regain by co-design!       √
                                                   NF marginally
                                                   Dynamic range marginally



                                                  Small value
           Current sensing: HF transient
           current has performance info

Fault-Tolerant Design of RF Front end Circuitry
                          Non-intrusive sensing




         Eliminate resistor for circuits with source-degenerative coils
              No measurable intrusion on LNA performance
              Over a narrow-frequency range, the source-coil can provide similar
               current-information as the resistor

         Gain and S22 sensed from source coil of mixer: accounts
          for matching network

Fault-Tolerant Design of RF Front end Circuitry
                      Quantifying Specifications


                                                   Two-tonal approach
                                                  to quantify impedance
                                                  matching
                                                   Differential nature
                                                  removes dependence
                                                  on absolute values
                                                   Highly robust and
                                                  insensitive to process
                                                  variations and soft
                                                  faults in processing
         Gain sensed directly at mixer,          circuitry itself
          using a third tone.
         Peak-peak value of this signal is a
          direct measure of gain

Fault-Tolerant Design of RF Front end Circuitry
                    Variable S11: The tapped coil
                                     Dependence of
                                                                        Varactor cannot be
                                     gain, etc. on gm
                                                                        connected in series

                                                          Magnitude
                                                          of match


                                                  g m Ls                       1
                                           Z in          j ( ( Ls  Lg )       )
                                                  CGS                         CGS
 Digitally tapped
gate inductor
 ASITIC – Include all
interconnects                                 Varies match frequency
 Switch size: trade-
                                              Tap the coil at several points in outer turn
off between on-
                                              CMOS Switches
                                              Include switch and interconnect parasitics
resistance and
capacitance

Fault-Tolerant Design of RF Front end Circuitry
                           Variable Gain and S22

                                                     S22: Bank of
                                                      varactors at output
                                                      node
                                                     Gain: Variable
                                                      Transconductance
                                                      array



                                                  ‘Current-splitting’ variable
                                                  transconductance array
                                                  eliminates S11 dependency:
                                                  CGS remains constant on
                                                  input-side


Fault-Tolerant Design of RF Front end Circuitry
                       Self-correction algorithm




     Minimal overheads
           No DSP, ADC or analog memory cell requirements, low power
     Ultra-fast, Low cost                                    VIDEAL

Fault-Tolerant Design of RF Front end Circuitry
                                   Sensor chain




            SF             Cascaded CS Stages     Peak Detector


                  Source follower for isolation
                  More stages for higher gain
                  PD output stored on capacitors
                  Op-amps for buffers, comparators
                  Basic digital logic

Fault-Tolerant Design of RF Front end Circuitry
                          Results - Sensor chain

                                                    Tap no.     sensor chain o/p    sensor chain o/p for
                                                                       for            tone2(2.2GHZ)
                                                                 tone1(1.6GHZ)
                                                      1           1098.54 mV            1391.57 mV
                                                      2            1112.85 mV           1375.63 mV
                                                      3           1128.67 mV            1365.23 mV
                                                      4           1150.61 mV            1356.95 mV
    Spectral response of sensor chain
                                                      5           1166.88 mV            1355.01 mV

                                                          Output of Sensor Chain for all taps of Lg




                       0.4 mV charge
                       leakage for 1V
                                          1000mv
                                          999.6mv




                                                              Transfer characteristic of the sensor chain.
      Charge leakage is negligible due to the                 The sensor chain delivered a gain of 9.4 at
               presence of buffers                               room temperature, nominal process.

Fault-Tolerant Design of RF Front end Circuitry
                                Simulation results - LNA

                           S11 after correction
                                                                                    S11 after
                                                                                    correction



          S11 before                                                                              S11 before
          correction                                                                              correctio
                                                                                                  n
                                            Desired S11
                                                                                                 Desired
                                                                                                 S11




            LG increase by 10%                                            CGS reduction by 15%
               S11 after correction



                                                                    Time taken per tap:1.75
                                                          Weakest      μs, per cycle: 6.2 μs,
                                                           corner      Total: 18.7 μs.
       S11 before correction


                                            Desired S11
                                                                    Worst-case scenario: all
                                                                      five cycles, 21.75 μs
Fault-Tolerant Design of RF Front end Circuitry
                  Experimental Results                       (1)




                                               Less   than 10% of LNA area
                                                  Re-used   for other front-end circuits
                                               Turned   on only during
                                                         correction process




                                                  Spectral response




                S11: -23 Front
Fault-Tolerant Design of RF dB end Circuitry
                   Experimental Results                               (2)

                                                  Tap   Induct   Simulate   Digital   Measured
                                                  no.    ance     d S11     word      S11 freq
                                                                   freq
                                                   1    7.4 nH   1.7 GHz      00      1.7375 GHz

                                                   2     9 nH    1.91 GHz     01      1.925 GHz

                                                   3    10 nH    2.0 GHz      10       2.03 GHz

   Measured transfer curve of the sensor chain     4    11 nH    2.11 GHz     11      2.125 GHz




                                                        Tapped Coil performance


                                                           S11 magnitude stayed
                                                           below -20 dB for all taps

                                                           Match frequencies were:
                                                           1.737 GHz, 1.925 GHz,
                                                           2.03 GHz and 2.125 GHz.


Fault-Tolerant Design of RF Front end Circuitry
                       S22 and Gain correction (I)


                                                  Left: S22 curves as varactor
                                                         Bank is varied

                                                  Right: Output spectrum of
                                                  Sensor for these S22 curves




                                                    Left: Gain and S22 match
                                                        varies as the load
                                                      inductor value varies

                                                  Right: Output of sensor chain
                                                        quantifying this
                                                           variation


Fault-Tolerant Design of RF Front end Circuitry
                     S22 and Gain Correction (II)


                                                       Self-calibration of S22:
                                                        Before (1.81 Ghz) and
                                                          After (1.89 GHz),
                                                         for a 1.9 GHz LNA




                                                  Left: Variation in the magnitude
                                                      of Gain (due to Q-factor
                                                      variation of the load coil)

                                                       Right: This Variation
                                                       quantified by sensor




Fault-Tolerant Design of RF Front end Circuitry
                                     Overheads


     Same circuitry re-used for all specifications
         Area overhead less than 10% of cascode LNA
         Can be re-used for other circuits of Front-end

     Losses in switches of the gate-coil
         NF    degradation by 0.2 - 0.3 dB
     Power overheads
         Additional circuitry switched on only for duration of self-
          calibration – negligible power overhead
         Current-splitting transconductance array uses additional
          current (5% - 10% overhead)



Fault-Tolerant Design of RF Front end Circuitry
                                       Summary

   Fault-tolerant RF design has great relevance and
    applicability in an RFIC world of increasing
    complexity and massive integration
   Alternate, novel methodology for fault-tolerance
    in GHz domain
   Minimal overheads, no topological revision
   Ultra-fast (200 us) compared to existing test
    schemes (order of 100s of ms)
   Robust algorithms and post-processing
    techniques
   Demonstrated in silicon

Fault-Tolerant Design of RF Front end Circuitry
                              Publications           (1)

Journal Papers
   Tejasvi Das, Anand Gopalan, Clyde Washburn and P.R. Mukund, “Self-calibration
    of RF front end circuitry”, IEEE Transactions on Circuits and Systems, Dec 2005
   Tejasvi Das, Anand Gopalan, Clyde Washburn and P.R. Mukund, “Towards Fault-
    tolerant RF front-ends”, Journal of Electronic Testing (JETTA), Accepted for
    publication (Issue release Sep.06)
   Anand Gopalan, M. Margala and P.R. Mukund, “A current based self-test
    methodology for RF front-end circuits”, Microelectronics Journal, No.36, Aug 2005
   Anand Gopalan, Tejasvi Das, Clyde Washburn and P.R. Mukund, “BiST for Multi-
    GHz CMOS RF Front-ends”, IEEE Transactions on Circuits and Systems (Under
    review)


Conference Papers
   “Self-calibration of Gain and Output match in LNAs”, IEEE ISCAS May 2006, Kos,
    Greece
   “Towards Fault-Tolerant RF Front-Ends: On-Chip Input Match Self-Correction of
    LNAs”, The IEEE Mixed-signal Test Workshop, June 2005, Cannes, France.
   “Dynamic Input match correction in RF Low Noise Amplifiers”, 19th IEEE
    International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct.
    2004, Cannes, France
Fault-Tolerant Design of RF Front end Circuitry
                              Publications          (2)

Conference papers (contd.)
   “Use of Source Degeneration for Non-Intrusive BIST of RF Front-end Circuits”,
    Proceedings of the International Symposium on Circuits and Systems, Kobe,
    Japan, May 2005
   An Ultra-fast, on-chip BiST for RF LNAs”, 18th IEEE International Conference
    on VLSI Design, India, Jan. 2005.




Fault-Tolerant Design of RF Front end Circuitry
                              References                   (1)
   [1] B. Razavi, “RF CMOS transceivers for cellular telephony”, IEEE Communications
    Magazine, Vol. 41, No. 8, pp.144 – 149, August 2003.
   [2] B. A. Floyd, C.-M. Hung, K. K. O, “Intra-Chip Wireless Interconnect for Clock
    Distribution Implemented With Integrated Antennas, Receivers, and Transmitters”, IEEE
    Journal of Solid-State Circuits, vol. 37, no. 5, pp. 543-552, May 2002.
   [3] M.-C. F. Chang, V. P. Poychowdhury, L. Zhang, H. Shin, Y. Qian, “RF/Wireless
    Interconnect for Inter- and Intra-Chip Cpmmunications”, Proceedings of the IEEE, vol.
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   [4] J.M.V Santos Dos, J.M.M Ferreira, “Fault-tolerance: new trends for digital circuits”
    IEEE International Conference on Electronics, Circuits and Systems, Vol 3, pp. 237 –
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   [5] Michael S. Heutmaker, Duy K. Le, “Architecture for self-test of a wireless
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    Communications Magazine, Vol. 37, No. 6, pp. 98-102, June 1999.
   [6] Madhuri Jarwala, Duy Le, Michael S Heutmaker, “End-to-end test strategy for
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   [7] N. Nagi, A. Chatterjee, H. Yoon, J. A. Abraham, “Signature analysis for analog and
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   [8] Rajsuman R., “Iddq testing for CMOS VLSI”, Proceedings of the IEEE, Vol.88 No. 4,
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Fault-Tolerant Design of RF Front end Circuitry
                              References                    (2)
   [9] Isern E., Figueras J., “Test generation with high coverages for quiescent current
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    2005, pp.485 – 490
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   [12] M. Soma, “Challenges and approaches in mixed signal RF testing” Proceedings of
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   [14] Yu.V Malyshenko, “Functional fault models for analog circuits”, IEEE Design & Test
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   [15] Anand Gopalan, P.R.Mukund and Martin Margala, “A Non-Intrusive Self-Test
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   [16] Thomas H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits”,
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Fault-Tolerant Design of RF Front end Circuitry
                               Thank You




Fault-Tolerant Design of RF Front end Circuitry

				
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