# Pengantar Organisasi Komputer IKI20210 Pengantar Organisasi Komputer Kuliah No 23 Aritmatika Sumber 1

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```					                  IKI20210
Pengantar Organisasi Komputer
Kuliah No. 23: Aritmatika
Sumber:
1. Hamacher. Computer Organization, ed-4.
2. Materi kuliah CS61C/2000 & CS152/1997, UCB.

18 Desember 2002
Bobby Nazief (nazief@cs.ui.ac.id)
Johny Moningka (moningka@cs.ui.ac.id)

bahan kuliah: http://www.cs.ui.ac.id/~iki20210/

1
Number Representation

2

Unsigned Numbers
° Decimal:
great for humans, especially              Dec Hex Binary
when doing arithmetic                     00   0   0000
01   1   0001
° Hex:                                      02   2   0010
if human looking at long                  03   3   0011
strings of binary numbers, its            04   4   0100
much easier to convert to hex             05   5   0101
06   6   0110
and look 4 bits/symbol                    07   7   0111
• Terrible for arithmetic; just say no   08   8   1000
09   9   1001
° Binary:                                   10   A   1010
what computers use;                       11   B   1011
12   C   1100
you learn how computers do                13   D   1101
+,-,*,/                                   14   E   1110
• To a computer, numbers always          15   F   1111
binary

3
How to Represent Negative Numbers?

° So far, unsigned numbers
° Obvious solution: define leftmost bit to be sign!
• 0 => +, 1 => -
• Rest of bits can be numerical value of number

° Representation called sign and magnitude

4
Shortcomings of sign and magnitude?

° Arithmetic circuit more complicated
• Special steps depending whether signs are the same or not

° Also, Two zeros
• 0x00000000 = +0ten
• 0x80000000 = -0ten
• What would it mean for programming?

° Sign and magnitude abandoned

5
Another try: complement the bits

° Example: 710 = 001112       -710 = 110002
° Called one’s Complement
° Note: postive numbers have leading 0s, negative

00000   00001 ...    01111

10000 ... 11110 11111

° What is -00000 ?
° How many positive numbers in N bits?
° How many negative ones?
6
Shortcomings of ones complement?

° Arithmetic not too hard

° Still two zeros
• 0x00000000 = +0ten
• 0xFFFFFFFF = -0ten
• What would it mean for programming?

° One’s complement eventually abandoned because
another solution was better

7
Search for Negative Number Representation

° Obvious solution didn’t work, find another
° What is result for unsigned numbers if tried to subtract
large number from a small one?
• Would try to borrow from string of leading 0s,
so result would have a string of leading 1s
• With no obvious better alternative, pick representation that made the
• 000000...xxx is >=0, 111111...xxx is < 0

° This representation called two’s complement

8
Two’s Complement Number line

11111    00000 00001    ° 2 N-1 non-negatives
11110               00010 ° 2 N-1 negatives
-1 0 1
-2         2        ° one zero
° how many positives?
.                        .     ° comparison?
.                        .
.                              ° overflow?
.

-15 -16 15
10001 10000 01111

9
Two’s Complement Numbers
0000 ... 0000   0000 0000 0000two =                                      0ten
0000 ... 0000   0000 0000 0001two =                                      1ten
0000 ... 0000   0000 0000 0010two =                                      2ten
...
0111 ... 1111   1111   1111   1101two =                   2,147,483,645ten
0111 ... 1111   1111   1111   1110two =                   2,147,483,646ten
0111 ... 1111   1111   1111   1111two =                   2,147,483,647ten
1000 ... 0000   0000   0000   0000two =                  –2,147,483,648ten
1000 ... 0000   0000   0000   0001two =                  –2,147,483,647ten
1000 ... 0000   0000   0000   0010two =                  –2,147,483,646ten
...
1111 ... 1111   1111 1111 1101two =                                  –3ten
1111 ... 1111   1111 1111 1110two =                                  –2ten
1111 ... 1111   1111 1111 1111two =                                  –1ten
° One zero, 1st bit => >=0 or <0, called sign bit
• but one negative with no positive –2,147,483,648ten

10
Two’s Complement Formula

° Can represent positive and negative numbers in terms of
the bit value times a power of 2:
• d31 x -231 + d30 x 230 + ... + d2 x 22 + d1 x 21 + d0 x 20

° Example
1111 1111 1111 1111 1111 1111 1111 1100two
= 1x-231 +1x230 +1x229+... +1x22+0x21+0x20
= -231 + 230 + 229 + ... + 22 + 0 + 0
= -2,147,483,648ten + 2,147,483,644ten
= -4ten

° Note: need to specify width: we use 32 bits

11
Two’s complement shortcut: Negation

° Invert every 0 to 1 and every 1 to 0, then add 1 to the
result
•   Sum of number and its one’s complement must be 111...111two
•   111...111two= -1ten
•   Let x’ mean the inverted representation of x
•   Then x + x’ = -1  x + x’ + 1 = 0  x’ + 1 = -x

° Example: -4 to +4 to -4
x : 1111 1111 1111 1111 1111 1111 1111 1100two
x’: 0000 0000 0000 0000 0000 0000 0000 0011two
+1: 0000 0000 0000 0000 0000 0000 0000 0100two
()’: 1111 1111 1111 1111 1111 1111 1111 1011two
+1: 1111 1111 1111 1111 1111 1111 1111 1100two

12
Two’s comp. shortcut: Sign extension

° Convert 2’s complement number using n bits to
more than n bits
° Simply replicate the most significant bit (sign bit)
of smaller to fill new bits
•2’s comp. positive number has infinite 0s
•2’s comp. negative number has infinite 1s
sign extension restores some of them
•16-bit -4ten to 32-bit:
1111 1111 1111 1100two
1111 1111 1111 1111 1111 1111 1111 1100two

13

14

Carries
a:          0       0       1        1
b:          0       1       0        1
Sum: 1              0       0        0

° Thus for any bit of addition:
• The inputs are ai, bi, CarryIni
• The outputs are Sumi, CarryOuti

° Note: CarryIni+1 = CarryOuti

15

Definition
A     B CarryIn CarryOut Sum
0     0    0        0     0
0     0    1        0     1
0     1    0        0     1
0     1    1        1     0
1     0    0        0     1
1     0    1        1     0
1     1    0        1     0
1     1    1        1     1

¯¯      ¯ ¯      ¯¯
Sum = ABCin + ABCin + ABCin + ABCin
CarryOut = AB + ACin + BCin
16

° To create one-bit full adder:
• implement gates for Sum
• implement gates for CarryOut
• connect all inputs with same name

CarryIn

A
+       Sum
B

CarryOut

17

CarryIn0
A0          1-bit       Sum0
B0           FA
CarryIn1 CarryOut0
A1          1-bit       Sum1
B1           FA
CarryIn2 CarryOut1
A2          1-bit       Sum2
B2           FA
CarryIn3 CarryOut2
A3         1-bit            Sum3
B3          FA

CarryOut3

° Critical Path of n-bit Rippled-carry adder is n*CP
• CP = 2 gate-delays (Cout = AB + ACin + BCin)

18
Overflow

° Binary bit patterns above are simply representatives
of numbers
° Numbers really have an infinite number of digits
• with almost all being zero except for a few of the rightmost digits
• Just don’t normally show leading zeros

° If result of add (or -,*/) cannot be represented by these
rightmost HW bits, overflow is said to have occurred
• When CarryOut is generated from MSB

00000 00001 00010                             11110 11111

19

20
Carry Look Ahead: reducing Carry Propagation delay

Cin                         A   B    C-out
0   0    0     “kill”
A0           S0                          0   1    C-in “propagate”
B0      G                                1   0    C-in “propagate”
P                                1   1    1     “generate”
C1 = G0 + C0  P0
= A0B0 + C0(A0+B0)
A            S                                   P=A+B
B       G                                        G=AB
P
C2 = G1 + G0 P1 + C0  P0  P1
A            S
B       G
P
C3 = G2 + G1 P2 + G0  P1  P2 + C0  P0  P1  P2
A            S
G                              G = G3 + P3·G2 + P3·P2·G1 + P3·P2·P1·G0
B
P                              P = P3·P2·P1·P0

C4 = . . .
21

° Expression for any carry:
• Ci+1 = Gi + PiGi-1 + … + PiPi-1 … P0C0

° All carries can be obtained in 3 gate-delays:
• 1 needed to developed all Pi and Gi
• 2 needed in the AND-OR circuit

° All sums can be obtained in 6 gate-delays:
• 3 needed to obtain carries
• 1 needed to invert carry                         ¯ ¯      ¯¯
Sum = ¯ ¯ in + ABCin + ABCin + ABCin
ABC
• 2 needed in the AND-OR circuit of Sum’s circuit

° Independent of the number of bits (n)
• CLA: 6 gate-delays                  • CLA: 6 gate-delays
• RC: (3*2 + 3) gate-delays           • RC: (15*2 + 3) gate-delays

22

C       C0
L
A    G0
P0
C1 = G0 + C0  P0

4-bit                              Delay = 3 + 2 + 3 = 8
Adder                              DelayRC = 15*2 + 3 = 33

C2 = G1 + G0 P1 + C0  P0  P1

4-bit

C3 = G2 + G1 P2 + G0  P1  P2 + C0  P0  P1  P2
G
4-bit                         P

C4 = . . .                                23

24

• Just add the two numbers               • Form 2’s complement of the
subtrahend
• Ignore the Carry-out from MSB
• Add the two numbers as in
• Result will be correct, provided         Addition
there’s no overflow

0 1 0 1 (+5)       0 1 0 1 (+5)      0 0 1 0 (+2)     0010
+0 0 1 0 (+2)      +1 0 1 0 (-6)     0 1 0 0 (+4)    +1 1 0 0 (-4)
0 1 1 1 (+7)       1 1 1 1 (-1)                       1 1 1 0 (-2)

1 0 1 1 (-5)       0 1 1 1 (+7)       1 1 1 0 (-2)     1110
+1 1 1 0 (-2)      +1 1 0 1 (-3)      1 0 1 1 (-5)    +0 1 0 1 (+5)
11 0 0 1 (-7)      10 1 0 0 (+4)                       10 0 1 1 (+3)

25
Overflow
Decimal       Binary                 Decimal       2’s Complement
0       0000                      0                 0000
1       0001                     -1                 1111
2       0010                     -2                 1110
3       0011                     -3                 1101
4       0100                     -4                 1100
5       0101                     -5                 1011
6       0110                     -6                 1010
7       0111                     -7                 1001
-8                 1000
° Examples: 7 + 3 = 10 but ...
°                  -4  5 = -9          but ...
0     1       1   1                         1
0       1   1        1     7                 1      1          0   0    –4
+         0       0   1        1     3         +       1      0          1   1    –5

1       0   1        0     –6                0      1          1   1        7

26
Overflow Detection

° Overflow: the result is too large (or too small) to represent
properly
• Example: - 8 < = 4-bit binary number <= 7
° When adding operands with different signs, overflow cannot
occur!
• 2 positive numbers and the sum is negative
• 2 negative numbers and the sum is positive
° On your own: Prove you can detect overflow by:
• Carry into MSB ° Carry out of MSB

0   1   1     1                       1    0
0   1     1     1   7                  1   1    0     0    –4
+       0   0     1     1   3            +     1   0    1     1    –5

1   0     1     0   –6                 0   1    1     1        7

27
Overflow Detection Logic

° Carry into MSB ° Carry out of MSB
• For a N-bit Adder: Overflow = CarryIn[N - 1] XOR CarryOut[N - 1]
CarryIn0

A0          1-bit      Result0         X       Y      X XOR Y
B0           FA
0      0           0
CarryIn1 CarryOut0
A1                                      0      1           1
1-bit      Result1
FA                         1      0           1
B1
1      1           0
CarryIn2 CarryOut1
A2          1-bit            Result2
B2           FA
CarryIn3
A3                                              Overflow
1-bit            Result3
B3           FA

CarryOut3

28

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