Galfa Spectrometer

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					           Galfa Spectrometer
                   Jeff Mock, Dan Werthimer
Students: Henry Chen, Pavel Monat, Aaron Parsons, Wonsop Sim
      Science Advisors: Carl Heiles, Snezana Stanimirovic




               http://seti.berkeley.edu/galfa
Image Rejection


• 45 dB   at +- 10 MHz
• 40 dB   at +-20 MHz
• 35 db   at +-30 MHz
Gain Control
• 0 to 40 dB gain – each of 16 channels
  – (2 spare IF to baseband converters)

• Controlled by RS232 serial port
• Overflow/Saturation detection
• Remote Operation (Displays as well)
GALFA Spectrometer
  Multi-Purpose FPGA-Based
  Spectrometer (NSF, A. Parsons)
                         200 Aux. I/O
           I   200 Mhz
                 ADC


     {
Pol. 1

         Q     200 Mhz
                 ADC                       Xilinx
 Arecibo                     Xilinx
                                          Virtex-II
  Feed                   Virtex-II 6000
  Array
                                            1000
                             FPGA
           I   200 Mhz                     FPGA
                 ADC

Pol. 2   {                                Compact PCI
                                           Backplane
         Q     200 Mhz
                 ADC

                         256 MB DRAM
                                           Software
FPGA-Based
Spectrometer

compactPCI
  •Power
  •Cooling
  •Robust/Reliable
  •Inexpensive
SETI Applications
•   ALFA Sky Survey (300 MHz x 7 beams)
•   Parkes Southern SERENDIP
•   JPL/UCB/SI Survey (20 GHz Bandwidth)
•   SETI Italia (Bologna)
•   SETI@home

Astronomy Applications
•   GALFA Spectrometer – Arecibo Multibeam Hydrogen Survey
•   Astronomy Signal Processor – ASP – Backer/Stairs (pulsars)
     – GreenBank and Arecibo, soon Nancay
•   ATA4 Correlator F Engine
•   Two Reionization Experiments
     (Backer/Demorest/Peeks (UCB), Chippendale/Green/Ekers (ATNF))
    GALFA Spectrometer
             Quadrature                      Multipurpose Spectrometer Board
            Downconverter
               Board
                            -50 to +50 MHz
                    LPF
IF Pol. 1                                                          
                                                    Biplex
             sin                100 MHz            256 pnt.
                    LPF                              PFB
                                                                    
                                                                                                    cPCI
                                                                                                  Backplan
             cos                                          FIR Decimate
                                                                                                      e
                    LPF                                   LPF by 14
                                                                                                     to
IF Pol. 2                                                                            Detect        CPU
                                                                          Biplex
                                                e^-it                   8192 pnt.
             sin                100 MHz                   FIR Decimate
                    LPF                                   LPF by 14        PFB
                                                                                     Detect   
             cos            -50 to +50 MHz      e^-it
                                             Digital LO
PFB vs. FFT
PFB vs. FFT
PFB vs. FFT
GALFA Lowpass Filter
GALFA Lowpass Filter
GALFA 2v6000 FPGA Resource Budget
                                                Blockrams Multipliers
      Biplex 8k PFB
                4x overlap FIR                             16
                           Coefficient tables   16
                           delays               56
                8k pt decimating FFT                       3
                           Twiddle tables       2
                           delays               26
      Biplex 256 PFB
                4x overlap FIR                             16
                           Coefficient tables   4
                           delays
                256 pt FFT                                 18
                           Twiddle tables       2
                           delays
      Dual Complex Mixer                                   8
      Dual lowpass filter                                  49
      Dual 256 point (x41) accumulator          4
      Dual 8k point (x32) accumulator           32
      Dual wideband power                                  4
      Dual narrowband power                                4

      Total                                     142        118

      Chip resource                             144        144
GALFA Diagnostics
GALFA Diagnostics
GALFA Diagnostics
Integration Time
• 988 mS fixed (99% duty cycle)
• Spectra read out every second
• Integration starts 6 mS after 1 PPS
• Integration stops 6 mS before 1 PPS
• Timing accuracy +-10 nS wrt observatory
   Data Output

• Galfa.yyyymmdd.projname.sequence_number.FITS
• file written every 15 seconds (programmable)
• 0.5 Mbyte/sec (8 MByte files)
• Files written over NFS to file server
• 2*8K + 2*256 32 bit powers (42 bit accumulators)
• Time stamped (NTP), plus telescope data
   Worries, Weaknesses
• ADC on same board with Digital Electronics
      (spurs at +- 25.000000 MHz…)
• Dynamic Range Problems (Overflow/Saturation)
      (prog. gain/shifting, overflow detection)
• Unknown LO phase shift (0 or 180 degrees)
  between channels after power cycle
  – (LO is divided by two in downconverter)
Spectrometer Documentation
• Schematics, Cabling Diagrams
• Software (Source code)
• Users Manual
• Diagnostics
• About 100 Pages of stuff
• http://seti.berkeley.edu/galfa
Short Term Plans

• Tonight: Jeff Mock Arrives
• Monday – Thursday: Integration/Test
• Friday – Sunday:              Observe
• This week:        come and visit for demo
     feel, touch, and get to know your spectrometer
Long Term Plans

• Find ET
Future SETI Spectrometers
2015      4 THz      400 beams
                      10 GHz each
2020      128 THz    12,800 beams

2025      4000 THz   40,000 beams

2030      128,000 THz 1M beams
Astronomy Signal Processor – Don Backer
                           Server    GbE     PC PC P
100 MHz
                        w/ EDT card Switch   PC PC P
  Pol. 1

           SERENDIP V      Server    GbE     PC PC P
                        w/ EDT card Switch   PC PC P
           Polyphase
           Filter          Server    GbE     PC PC P
100 MHz
                        w/ EDT card Switch   PC PC P
  Pol. 2   Bank
                           Server    GbE     PC PC P
                        w/ EDT card Switch   PC PC P
SERENDIP V Spectrometer
            Biplex Pipelined FFT
            Example: 8 pnt. FFT

Time                                                                                         Frequency
Domain                Switch
                                                                                               Domain
Pol. 1                            -4                -2                        -1
                                Z                 Z                         Z
                               Coefficient
         Delay by N             Multiply
Pol. 2       -4                              -2                        -1                        -0
            Z                                Z                         Z                         Z
                                  Unity           2nd Roots of Unity        4th Roots of Unity
JFFT FFT controls
• Any length transform
• Input width and output width
• twiddle coefficient width
• 3 or 4 multiplier complex multiply
• Specify downshift or programmable downshift (optional
  rounding)
• Decimate FFT option
• Blockram / CLB memory threshold option
• Overflow detection
JFFT additional PFB controls
• Filter overlap
• Width of filter coefficients
• Window function for filter (hamming, hann, etc.)
• Import filter coefficients for custom filter performance
                                Moore’s Law in FPGA world
                                   Computational Density Comparison

                     10000000                                                               100X More efficient
                                     Processor Peak
(MOPS/MHz)*lamda^2




                      1000000        FPGA 32-bit int MAC                                    than micro-processors!
                       100000


                        10000

                                                                                                                                     FPGA maximum sustained performance
                         1000
                           10/28/19 3/11/199 7/24/199 12/6/199 4/19/200 9/1/2002 1/14/200                        100000
                              95        7        8        9        1                 4
                                                      Release Date                                                10000




                                                                                             MOPS (32 bit MAC)
                                                                                                                   1000


                                                                                                                    100


                                            3X improvement                                                           10


                                            per year!                                                                 1
                                                                                                                     12/1/19 6/19/19 1/5/199 7/24/19 2/9/199 8/28/19 3/15/20 10/1/20 4/19/20 11/5/20 5/24/20
                                                                                                                       96       97      8       98      9       99      00     00       01     01       02
                                                                                                                                                          Release date
Next Generation Board
BEE2 (2004/5) – Chen Chang
• 5 Xilinx XC2VP70
• 40 GB RAM (8 GB each chip, 13Gbit/sec/chip)
• 18 10Gbit/sec infiniband ports
• 50 boards per rack, Tbit/sec infiniband switch
• Applications:
   – 1 GHz, 1 Gchannel spectrometer (single board)
   – Next Generation ATA backends (ata32 = 2 boards)
   – SKA imaging
    B2 Module: board layout
• 5 compute
  elements on a
  board
• Up to 400 billion
  CMAC/s
  performance
• communication
  bandwidth:
   – 240 Gbps on-
     board 360 Gbps
     off-board
 Global Interconnects
                                         Ethernet Switch
• Commercial Infiniband
  switch from Mellanox,
  Voltaire, etc.               Compute
                                Node
                                                            Compute
                                                             Node
   – Packet switched, non-       #1                           #N
     blocking
   – 24 ~ 144 ports (4X) per
     chassis                        Infiniband Crossbar Switch
   – 480Gbps ~ 2.88Tbps
     full duplex constant
     cross section bandwidth
   – <$400 per port
      19” 48RU Rack CabinCapacity
• 40 compute nodes in 5 chassis
  (8U) per rack
• Up to 16 trillion CMac/s
  performance per rack
• 250 Watt AC/DC power supply
  to each blade
• 12.5 Kwatt total power
      Unified Digital Processing Architecture
             Polyphase   Channel
     An #1     Filter    Reorder                       XMAC           imaging
              Banks       Buffer




                                   Infiniband Swtich




                                                        Beamforming
                                                                                   Spectrometer




                                                                      Infiniband
                                                                        Swtich
             Polyphase   Channel
     An #N     Filter    Reorder
              Banks       Buffer                                                     Pulsar
                                                                                    Searching

•   Distributed per antenna spectral channel processing
•   Multiple reconfigurable backend application processing
•   Commercial packet switched interconnect
•   Backend data pulling through remote DMA access
Happy Birthday Carl

				
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posted:3/14/2012
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