# Copy of digital electronics

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```					                                                   MAHARANA INSTITUTE OF TECHNOLOGY & SCIENCES
GAURA , MOHANLALGANJ, LUCKNOW
LECTURE PLAN

Faculty Name: Amit Kumar Singh            Branch: EC          Semester: 3                     Session: 2010-11
Subject:      Digital electronics                   Subject Code: EEC 302

S.No.πLECTURE NO.     UNIT                                                   TOPICS TO BE COVERED                          REMARK

1      Lecture-1      1    Analog and digital systems, Number system, Binary arithmatic.

2      Lecture-2      1    Complements, Substraction through complements.

3      Lecture-3      1    Signed binary numbers,Signed binary arithmatic.

4      Lecture-4      1    Binary codes,Error detecting and correcting codes.

5      Lecture-5      1    Cyclic codes,floating point numbers.

6      Lecture-6      1    Logic gates, Boolean function, SOP and POS.

7      Lecture-7      1    K-map simplifications, Don't care conditions.

8      Lecture-8      1    Five variable k-map, NAND and NOR implementation.

9      Lecture-9      1    Quiene-Mc-Cluskey (Tabular method).

10     Lecture-10     1    Tabular method and related examples of UPTU.

Signature of Faculty
S.No.πLECTURE NO.    UNIT                                                   TOPICS TO BE COVERED                                                REMARK

11    Lecture-11    2     Combination logic circuits: Introduction, Analysis procedure,Design.

14    Lecture-14    2     Binary multiplier,Binary to BCD code converter.

15    Lecture-15    2     BCD to Excess-3,Excess-3 to BCD,Binary to gray,Gray to binary,Magnitude comparator.

16    Lecture-16    2     Decoders:2 to 4 binary decoder, 3 to 8 binary decoder, Expanding decoder, Applications of decoder.

17    Lecture-17    2     Encoders: Decimal to BCD encoders, Octal to binary encoder, Priority encoder.

18    Lecture-18    2     Multiplexer: 2:1 MUX, 4:1 MUX, 8:1 MUX, MUX applications.

19    Lecture-19    2     Demux: 1:4 DEMUX, 1:8 DEMUX, DEMUX applications.

20    Lecture-20    3     Synchronous sequential logic: Introduction, Latches, Flip flops, Clocked RS flip flop using NAND gates.

21    Lecture-21    3     J.K. flip flop, Master slave JK flip flop, Flip flops characterstic equations.

22    Lecture-22    3     Flip flop excitation tables, Flip flop conversion, Mealay sequential circuit.

23    Lecture-23    3     Moore sequential circuit, State assignment, Design procedure.

24    lecture-24    3     Sequence generator using counters, using shift registers.

Signature of Faculty
S.No.πLECTURE NO.    UNIT                                                   TOPICS TO BE COVERED                                                         REMARK

25    Lecture-25    3     Sequence detector, Solved examples.

26    Lecture-26    3     Registers and Counters: Introduction, Shift register, Classification of shift register.

27    Lecture-27    3     Various shift register, Universal shift register, Shift register applications.

28    Lecture-28    3     Counter: Basic concept, Asynchronous counter, 2 bit, 3bit, 4 bit asynchronous down counter.

29    Lecture-29    3     2 bit ripple up down , 3 bit up down, Design of N bit ripple counter.

30    Lecture-30    3     Synchronous counter: 2 bit, 3 bit, 4 bit, Design procedure, Mod-N.

31    Lecture-31    3     Lock out, up/down synchronous counter, Ring counter, Johnson counter.

32    Lecture-32    4     Memory and programmable logic: Introduction, Basics terms of memory, Basic memory operation.

33    Lecture-33    4     Memory classification, RAM , ROM, PLA, PAL.

34    Lecture-34    4     Register transfer level: Basic element of ASM , Definition related to ASM, Timing considerations.

35    Lecture-35    4     Design example: Control implementation, State table method, Design with MUX method.

36    Lecture-36    5     Asynchronous sequential logic: Introduction, fundamental mode circuits, Pulse mode circuits, Analysis procedure.

37    Lecture-37    5     Circuit with latches: SR latch using NOR gates, using NAND gate implementation.

38    Lecture-38    5     Design procedure: Derivation of Primitive flow table, State reduction techniques, State assignment.

Signature of Faculty
S.No.πLECTURE NO.    UNIT                                                 TOPICS TO BE COVERED                        REMARK

39    Lecture-39    5     Pulse mode asynchronous sequential circuits, Analysis, Design.

40    Lecture-40    5     Hazard : Hazard in combinaion logic circuit, Classification of static hazard.

41    Lecture-41    5     Essential hazard, Hazard in asynchronous sequential circuit, Solved examples.

42    Lecture-42

43    Lecture-43

44    Lecture-44          \

45    Lecture-45

46    Lecture-46

47    Lecture-47

48    Lecture-48

49    Lecture-49

50    Lecture-50

Signature of Faculty

```
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