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A “short list” of embedded systems Microprocessors and Interfacing Techniques

VIEWS: 17 PAGES: 47

									             Microprocessors and
            Interfacing Techniques

                    RM.Kuppan Chetty
                     Dr.Nilesh J Vasa

               Indian Institute of Technology Madras
                          Chennai - 600036



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    Interfacing Basics
    Memory Interfacing
    I/O Interfacing
    Serial and Parallel Interfacing




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Interfacing
    A microprocessor communicates with other memory
    banks/other devices using some of its pins and signals
    Designing the interfacing circuitry and address decoding
    for memory and I/O ports
    Two types
       Memory Interfacing
          To be able to read/write from memory
       I/O Interfacing
          To able to read/write from external devices through
          ports




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Components used along with UP while interfacing




      Buffer (Input Port)   Latch (output Port)       Decoder




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Memory Interfacing
    Select the chip
    Identify the register
    Enable the appropriate buffer
    Read/write from memory location
                             A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

                            0    0       0    0   0      0   0   0   0   0   0   0   0   0   0       0

                                     Chip select logic       1   1   1   1   1   1   1   1   1       1


                            Start address – 0000H
                            End address – 03FFH




                          Memory address range: 1024 Bytes of Memory




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                                                  Interfacing R/W memory


                                      4096 bytes of Memory location
                                      • needs 2n address lines to address
                                           •i.e needs 11 bits to address
                                      • remaining 4 bits of AD lines are used for chip
                                      select
                                      • Decoder is used to select the memory banks
  Address Decoding and Reading from
                                      • RD and WR is used as the control signals
              Memory




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Interfacing I/O devices
    Interfacing I/O devices such as Keyboards
    and Displays. Other peripherals like sensors,
    actuators and display devices
    Methods of I/O interfacing
            Parallel and Serial I/O interfacing
    Modes of Interfacing
            I/O mapped I/O – viewed as distinct I/O devices
             Memory – mapped I/O - viewed as memory locations




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Memory Mapped I/O vs I/O Mapped I/O
            I/O Mapped I/O            Memory mapped I/O
 8 bit address                  16 bits address
 256 ports can be interfaced Large no. of I/O ports upto1Mb
 IORD & IOWR signals            MEMR& MEMW signals
 IN and OUT Instns.             All memory related instns
 Comparatively simple           Decoding CKT is complex




    Block Diagram of I/O Interface

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                                                 • IOR is used as Control signal
                                                 • Tristate buffer is used as interfacing
                                                 port
                                                 • FFH is the Port address along with
                                                 the Control signal
                                                 • Inst. used is IN FFH




  Decode Logic for a DIP Switch
• IOR and IOW is used as Control
signal in RD and WR resp.
• Tristate buffer and Latch is used as
interfacing port
• FAH is the Port address for IOR and
F8H is for IOW
• Inst. used is IN FAH for IOR and
 OUT F8H is for IOW                        Decode Logic for a DIP Switch and LED O/P


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Memory Mapped I/O




Read: LDA FFF9H
            CMA
            STA FFF8H
            JMP Read

•MEMW and MEMR is used as control signal
•Direct interfacing without I/O
•74LS244 buffer is used as switch and 74LS373 latch is used as tristate o/p.
•FFF8H is the port address for O/P port and FFF9H is the I/P port address.

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Serial I/O and Interfacing
Serial Data Transfer – used by keyboards, plotters, modems and other
peripherals with low data transfer rates (low bandwidth)


2 Types:
      Asynchronous – CPU and device are not using a common time reference
             - no common clock/timing signal
             - special bit patterns indicate begin/end
             - slower than synchronous

      Synchronous – common time reference used
             - timing controlled
             - synchronization pulses related to a clock are sent/received
             - faster than asynchronous




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 Serial Port is 1-bit Parallel Port




LSB of Data Bus                    out   0,    al
                                   in    al,   0


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    In serial I/O, the data bits are sent one at a time across
    a single line.
        The advantage of serial I/O is lower cost (in terms of the
        number of wires connecting the microcomputer to peripheral
        device)
        The disadvantage is slower speed.

                                                               D




                                                 Processor




                                                                      I/O Device
                                                             Strobe




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Baud Rate vs Bits Per Second
       Baud rate is the rate at which signaling events are sent i.e is the number of symbol
       changes (signalling events) made to the transmission medium per second
            Typical baud rates are 300, 600, 1200, 1800, 2400, 3600, 4800, 7200, 9600,
            14400, 19200, 28800, 38400, or 57600
       Data rate (bits per second, bps) is number of bits transferred per second (any type
       of bits, whether data or overhead bits)
       If only a single bit (‘1’ or ‘0’, either of two levels) is sent for each signaling event,
       then baud rate = data rate (bps)
       If N no. of bits are sent in a each symbol then the value of bps is
                   Bps = Baud rate * N (i.e bits per baud)
                   Ex let 4 bits/symbol, with 300baud, then total bps = 4*300=1200bits/s;
       The effective data rate is the rate at which data is transferred, minus the framing
       overhead bits (i.e., start, stop, parity bits).




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Synchronous Data Transmission
    In Asynchronous data transmission TX and RX clocks
    are unsynchronised
            Inefficient (for each 7 bits we send 3 – 4 extra bits)
            Synhronisation across characters
    In Synchronous Data Transmission TX and RX clocks
    are synchronised
            A common shared clock, (I2C), or clocking information
            embedded in the data stream (USB, Ethernet)
            Fast (many bytes send before a re-synchronisation)
            Synchronisation across frames vs characters
                       one char
Asy                                 Start     7-bit data   stop




                       one frame

Syn
               Start

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Asynchronous Serial Communication
Used in character oriented data transmission between a
microprocessor and an external device
     Transmitter and Receiver each has its own clock running at the
     same frequency
     How to synchronize two clocks so to sample in the middle of the
     data?




  Data TX Clock             RX Clock
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Making Asyn. Transmission Work
Receiver Synchronisation:
     The transmission of first bit should starts with a
     transition on the data line (1 0)
     send an extra ‘start’ bit ( = 0) before sending the 8-bit
     data,
     data line is always set back to 1 at the end.
     1     0 transition always occurs at the start of each
     transmission.
     the receive clock now samples 9 bits (start + 8 data
     bits),
     the gap (idle time) between successive groups of 9
     bits can change
     Character wide synchronisation (Asynchronous)


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Receiver Clock Synchronization Issues
     The receiver clock can be made equal to the baud rate
     clock must be very accurate in order to sample the incoming bit
     stream in the centre of its cycle.
     The sample point needs to be very close to the centre of the bit
     cell for reliable data recovery.
     The actual variation from the centre on the bit cell is referred to
     as ratchet error.




                                                            RX Clock
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Standards in serial communication
    Data transmission is either through Current or Volatage (4-20mA, TTL)
    RS232, TTL, 20Kbaud, 50ft distance.
    Others are RS422A and RS423A
            RS422A – 10Mbaud for 40ft and 100Kbaud for 1000ft
            RS423A – 100Kbaud for 30ft and 10K baud for 300ft.
    Along with Microprocessors two pin SOD (serial Output Data) and SID
    (serial I/P Data) is used.)
    Instructions used are SIM (set Interrupt Mask) – Read SID Line, RIM
    (Read Interrupt Mask) – write SID line
    SIM – Output data serially and RIM – Input data serially
    8251 UART is used as a Hardware Controller for Serial I/O along with
    8085.



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8251 Programmable communication Interface




               Block Diagram of 8251

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    (a) Mode word format, (b) command word format, (c) status word format



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 Schematic Interfacing an RS232 Terminal with an 8085 system using 8251A




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    A7




    A0




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Limitations:
1. Output is 1 LSB less then the Full scale Reference voltage.
               n
2. Can have 2 combinations – n =3        8 combinations.
                                     n
3. Resolution - 1 LSB change – (1/ 2 )* VFS.

    An ALP to Generate a continuous waveform. ( saw tooth waveform)

            mov Al,00                     5v

 DtoA:      Out FF,al
 Loop:      Mov CX,count
                                            0
            Loop
                                                    Slope can be varied by
            INC Al
                                                    varying the delay
            Jmp DtoA




2009/3/30                      RMK-NJV-IITM-ED202                            29
Tutorial:
  Write an ALP to generate the following wave forms using DAC
          generate a square wave of 2Khz frequency.
          generate a triangular waveform of 200ms period.
          generate the given wave form


               5V


              2.5V



                                                 Time (ms)
                     100   200    75     75




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For selection – 10000010 – 82H – I/O write – Start conversion
                         80H – I/O read – EOC, 81H – Read the digital data

 2009/3/30                     RMK-NJV-IITM-ED202                            35
Critical parameters:
     • Conversion time.

     • Resolution : indicates the number of discrete values it can produce
     over the range of voltage values. It is usually expressed in bits.
                                 8
     Ex: 8 bit converter     2       256 (0-255).
     • The voltage resolution of an ADC is equal to its overall voltage
     measurement range divided by the number of discrete values.
                                                                   8
            For a Full scale measurement range of 0 – 10V    (10/ 2 ).
     • Quantization error:
     It is in the conversion of a discrete signal (a sampled continuous signal)
     into a digital signal. - finite resolution of the ADC
      represented interms of bits. Usually the value is less than half-LSB
     It can be reduced by increasing the no. of bits of the ADC


2009/3/30                            RMK-NJV-IITM-ED202                      36
Microprocessor Applications: Case Study
    A variety of applications from house hold to
    the real engineering problems.
            Temperature Control systems
            Dc motor Speed Control system
            Stepper motor control system
            Traffic Light Control system etc…




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Temperature Control system




            Block Diagram of 8085 based temperature control system




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    A Simple ON/OFF Control System
    Input param – temperature, set point.
    Output param - voltage to heating coil,
    display interface.
    Components required..
            ADC
            DAC
            Heating coil
            Temperature sensor
            8255, 8279 and 8085 along with latches and buffers.




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            Initialize
            1. 8255 in Input and output mode
            2.    ADC
            3.    DAC
            4.    Display interface




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DC motor speed control system




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Stepper motor control system




                                    Driver Circuit




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Full Step Mode
sequence        Clockwise rotation       Anticlockwise rotation
                PA3 PA2 PA1 PA0 PA3 PA2 PA1 PA0
Sequence 1      1       1       0   0    0    0      1     1         0CH 03H
Sequence 2      0       1       1   0    0    1      1     0         06H   06H
Sequence 3      0       0       1   1    1    1      0     0         03H   OCH
Sequence 4      1       0       0   1    1    0      0     1         09H   09H


Half Step Mode                                                                   MVI A,CWR
Clockwise rotation          Anticlockwise rotation                               OUT PCWR
PA3 PA2 PA1 PA0 PA3 PA2 PA1 PA0                                      Start:      MVI C, count – 04 for FSmode
1    1      0       0       0   0    1   1           0CH 03H
0    1      0       0       0   0    1   0           04H       02H               LXI H, XXXX
0    1      1       0       0   1    1   0           06H       O6H
                                                                     Loop:       MOV A,M
0    0      1       0       0   1    0   0           02H       04H
                                                     03H       0CH
                                                                                 OUT PA
0    0      1       1       1   1    0   0
0    0      0       1       1   0    0   0           01H       08H               INX H
1    0      0       1       1   0    0   1           09H       09H               Call delay
1    0      0       0       0   0    0   1           08H       01H
                                                                                 DCR C
                                                                                 JNZ loop
                                                                                 JMP start

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Traffic Light Control System




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Program             NORTH:                  SOUTH:
                          MVI C,03                MVI C,03
       MVI A, CWR         LXI H, 4000             LXI H, 4000
       OUT PCWR     LOOP: MOV A,M           LOOP: MOV A,M
START: CALL NORTH         OUT PA                  OUT PA
       CALL SOUTH         INXH                    INX H
       CALL EAST          MOV A,M                 MOV A,M
       CALL WEST          OUT PB                  OUT PB
       JMP START          INX H                   INX H
                          MOV A,M                 MOV A,M
                          OUT PC                  OUT PC
                          CALL DELAY              CALL DELAY
                          INX H                   INX H
                          DEC C                   DEC C
                          JNZ LOOP                JNZ LOOP
                          RET                     RET




2009/3/30              RMK-NJV-IITM-ED202                       47

								
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