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Fundamental Limits of Positron Emission Mammography

VIEWS: 3 PAGES: 31

									            Data Acquisition Electronics
                        for
           Positron Emission Tomography
                        William W. Moses
               Lawrence Berkeley National Laboratory
                          May 24, 2010
           Outline:
           • PET Overview
           • PET Electronics Requirements & Trends
           • OpenPET Electronics
• This work was supported in part by the U.S. DOE (contract No. DE-AC02-05CH11231)
  and in part by the NIH (NIBIB grant No. R01-EB006085).
• Thanks to S. Choong, C. Vu, and Q. Peng of LBNL, C. Jackson, S. Buckley, and N.
  Pavlov of SensL, M. Casey and J. Young of Siemens Medical Solutions, D. McDaniel of
  GE Medical Systems, and J. Karp of U. Penn.
 Nuclear Medicine
         • Patient injected with small
           amount of radioactive drug.
         • Drug localizes in patient
           according to metabolic
Gamma      properties of that drug.
Camera   • Radioactivity decays,
           emitting gamma rays.
         • Gamma rays that exit the
           patient are imaged.
•Well Established Clinical Technique
    •10 Million Studies Annually
     Positron Emission Tomography (PET)
Ring of Photon
Detectors
                      • Radionuclide decays by
                        emitting a positron (+ ).
                      • + annihilates with e– from
                        tissue, forming back-to-back
                        511 keV photon pair.
                      • 511 keV photon pairs detected
                        via time coincidence.
                      • Positron lies on line defined by
                        detector pair.

• Detects Pairs of Back-to-Back 511 keV Photons
• Use Computed Tomography to Form 2-D Image
 MRI & PET Images of Epilepsy




  MRI                                PET
 • MRI “Sees” Structure with 0.5 mm Resolution
• PET “Sees” Metabolism with 4.0 mm Resolution
    Combine PET & CT (Oncology)
CT Image    PET Image   Fused Image               Post-Therapy




                        Images courtesy of Stig Larsson, Karolinska Institute

  • Anatomy from X-Ray CT, Function from PET
          • Current “Standard of Care”
  Combine PET & CT (Cardiac)




                                  Image courtesy of
                                  Gustav von Schulthess,
                                  University Hospital, Zurich


Anatomy from X-Ray CT, Function from PET
           What Is A “PET Event”?
          (What Do You Need To Record?)




• Non-TOF PET: A Chord — Defined By Two End Points
        • Time-of-Flight PET: A Chord and t
     What Is The Electronics Concept?
                           “Singles Event”
                           • Position (crystal of interaction)
                           • Time Stamp (arrival time)
                           • Energy Validation (=511 keV?)

                                                         t
                           “Singles Event”
                           • Position (crystal of interaction)
                           • Time Stamp (arrival time)
                           • Energy Validation (=511 keV?)

                • Identify “Singles Events”
• Find Time Coincidences Between Singles Events w/ t
  • “Coincident Event” = Pair of Singles Events (Chord)
                    Numbers

• 150-300 Detector Modules (25 cm2 each) per Camera
• 100 kHz Typical Singles Rate per Module
• 1 MHz Maximum Singles Rate per Module
• 1 MHz Typical Coincidence Rate per Camera
• 4 MHz Maximum Coincidence Rate per Camera
• 1 ns fwhm Timing Resolution for Conventional PET
• 250 ps fwhm Timing Resolution for TOF PET

       • Low Coincidence / Singles Ratio
  • Low Occupancy in Each Detector Module
            Multiplex Singles Events
                       PET Detector Module
                                           Profile
Array of Scintillator Crystals             through
                                           Row 2




                                            Y-Ratio




                   Photomultiplier Tubes
                                                      X-Ratio

Decode Crystals Using Anger Logic (Light Sharing)
                         Position Identification
     1   2   3   4   5   6   7          1    2        3     4     5     6    7
     8   9   10 11 12 13 14             8    9        10    11    12    13   14
         A
     15 16 17 18 19 20 21B
                                        15   16       17    18    19   20    21
     22 23 24 25 26 27 28
     29 30 31 32 33 34 35
     36 37 38 30 40 41 41           Y   22       23    24    25   26   27    28

         C
     43 44 45 46 47 48 49D              29       30    31    32   33   34    35
     50 51 52 53 54 55 56

                                        36   37        38    39   40   41    42

    E=A+B+C+D                           43   44       45    46    47   48    49
     Y=(A+B)/E                          50   51       52    53    54    55   56

     X=(B+D)/E                          X
•Identify Crystal of Interaction Using Lookup Table
           •Position Given by Crystal ID
                            Energy Validation
                         14000

                         12000             No              Yes      No


        Counts per Bin
                         10000

                          8000

                          6000

                          4000

                          2000

                             0
                                 0   100      200    300      400   500
                                           Pulse Height Bin

                     E
•Yes/No Decision Based on Measured Energy
   •Individual Thresholds for Each Crystal
      •Implemented Using Lookup Table
                        Time Stamp

Detector Module                 TDC             From Central Timing Board

                  CFD    Stop          Clock        Master Clock


                                Start / Reset       Time Slice Boundary



            • “Raw” Time Stamp is Digitized Time
                Since Last Time Slice Boundary
              • Each Crystal Assumed to Have a
         Different (But Constant) Propagation Delay
    • Propagation Delays Measured w/ Positron Source
               and Stored in a Lookup Table
• Crystal by Crystal Correction Factor Added to “Raw” Time
               Identifying Time Coincidences

     Slice 1             Slice 2               Slice 3       Slice 4          Slice 5         Slice 6
                              Not Coincidence                  Coincidence
 Coincidence                                                                              Coincidence
                                  Single Coincidence                        Single                    Single
   Single                                                          Single                      Coincidence
                                                                                            Single
                                                 Single
            Single       Single                                                  Single
                                                          Single   Single                        Single
                                      Single                                                Single
   Single       Single       Single              Single        Single
                                                                             Single              Single




                                          Time

   tmax
      • Break Time Into Slices (100–250 ns / slice)
• Search for Singles Within tmax (4–12 ns) in Each Slice
            • Greatly Reduces Combinatorics
   Siemens & GE Detector Topology



 Scintillator
Crystal Array




        • 4 PMTs to Decode Event Position
  • Independent Modules Operating in Parallel
            Siemens & GE System Architecture

                       Position                 Position
            Detector              Multiplexer
             Board      Time                     Time
                                   Board
             Energy


                                                                         Chord
Detectors
                                                           Coincidence           Host PC


                       Position                 Position
            Detector              Multiplexer
             Board      Time                     Time
                                   Board
             Energy



    • Position, Time, & Energy Computed for Each Trigger
        • All Data Flow is Forward  No Handshaking
          Philips Detector Topology



   Scintillator
  Crystal Array




         • 7–20 PMTs to Decode Event Position
• Highly Coupled—Each PMT Used in Many “Modules”
                 Philips System Architecture
                                 ADC Output

            Detector   Coincidence
             Board                                            Position
                          Time
                                                              Energy

                                                   PMT ID                Chord
Detectors                            Coincidence            Processing           Host PC
                                        Board                 Board

                                                             Position
            Detector      Time
             Board                                            Energy
                       Coincidence

                                 ADC Output

    • Position & Energy Computed Only for Coincidences
           • Bidirectional Data Flow  Handshaking
           Typical Front End Architecture
    PMTs
                                                                Logic
               Gain Adjust,
A               Integrate     A+B
                              Sum         Vin         Y     Crystal Lookup
                                                ADC          (X & Y  ID)
               Gain Adjust,               Vref
B               Integrate     B+D
                              Sum         Vin         X        Energy
               Gain Adjust,                     ADC           Validation
                                          Vref
C               Integrate                                  (E & ID  511?)

                                          Vin         E
               Gain Adjust,                     ADC
D                                   +5V   Vref                Time Stamp
                Integrate                                 (T & ID  T Stamp)

                                                      T
                Sum           CFD            TDC           Event Formatting


    Corrections Done In Real Time, Outputs Singles Events
           Siemens Implementation (~1995)
    PMTs
                                                             Custom ASIC
                Gain Adjust,
A                Integrate     A+B
                               Sum         Vin         Y     Crystal Lookup
                                                 ADC          (X & Y  ID)
                Gain Adjust,               Vref
B                Integrate     B+D
                               Sum         Vin         X        Energy
                Gain Adjust,                     ADC           Validation
                                           Vref
C                Integrate                                  (E & ID  511?)

                                           Vin         E
                Gain Adjust,                     ADC
D                                    +5V   Vref                Time Stamp
                 Integrate                                 (T & ID  T Stamp)

                                                       T
                Sum            CFD            TDC           Event Formatting


    Analog Done w/ Discretes, Digital Done w/ Custom ASIC
           Siemens Implementation (~2000)
    PMTs          Custom ASIC
                                                           FPGA & Memory
               Gain Adjust,
A               Integrate     A+B
                              Sum         Vin         Y     Crystal Lookup
                                                ADC          (X & Y  ID)
               Gain Adjust,               Vref
B               Integrate     B+D
                              Sum         Vin         X        Energy
               Gain Adjust,                     ADC           Validation
                                          Vref
C               Integrate                                  (E & ID  511?)

                                          Vin         E
               Gain Adjust,                     ADC
D                                   +5V   Vref                Time Stamp
                Integrate                                 (T & ID  T Stamp)

                                                      T
               Sum            CFD            TDC           Event Formatting


     Analog Done w/ Custom ASIC, Digital Done w/ FPGA
           Siemens Implementation (~2005)
    PMTs      Custom ASIC             Free-Running
                                        (~75 MHz)               FPGA & Memory
               Gain Adjust,
A               Anti-Alias                Vin          A
                                                ADC
                                    +5V   Vref                   Crystal Lookup
                                                                  (X & Y  ID)
               Gain Adjust,
B               Anti-Alias                Vin          B
                                                ADC
                                    +5V   Vref
                                                                    Energy
               Gain Adjust,                                        Validation
C               Anti-Alias                Vin          C        (E & ID  511?)
                                                ADC
                                    +5V   Vref

               Gain Adjust,                                        Time Stamp
D               Anti-Alias                Vin          D
                                                ADC            (T & ID  T Stamp)
                                    +5V   Vref

                                                           T
               Sum            CFD                TDC            Event Formatting


Op-AmpFree Running ADC, More Digital Done w/ FPGA
• Nuclear Medicine Research Community Needs
  “Industrial-Strength” Electronics
• Needs Can Be Met By Single, Flexible Design!
     Electronics System Requirements
High-Performance
  •# of Channels, Rate, Energy, Timing, …
Very Flexible
  •Type of Detector, Camera Configuration,
   Event Word Definition
User-Modifiable
  •Schematics, Source Code, Knowledge Base
User-Friendly
  •Instructions, Documentation, Can Buy Boards

   Like Open Source Software!
     All Detector Outputs Look the Same

    Extract Timing Signal          Extract “Energy” from
    from Leading Edge              Area Under the Curve

Voltage

                                       100 mV – 2 V




                            Time
  • Tremendous Variation in How Outputs Are Combined
            Combine Outputs in Firmware
           OpenPET Implementation (~2010)
    PMTs                         Free-Running
                                   (80 MHz)
               Gain Adjust,                                 FPGA & Memory
                                     Vin
A               Anti-Alias                 ADC
                               +5V   Vref              A
               Discriminator                     TDC         Crystal Lookup
                                                              (X & Y  ID)
               Gain Adjust,
                                     Vin
B               Anti-Alias                 ADC
                               +5V   Vref              B
               Discriminator                                    Energy
                                                 TDC           Validation
               Gain Adjust,                                 (E & ID  511?)
                                     Vin
C               Anti-Alias                 ADC
                               +5V   Vref              C
               Discriminator                     TDC           Time Stamp
                                                           (T & ID  T Stamp)
               Gain Adjust,
                                     Vin
D               Anti-Alias                 ADC
                               +5V   Vref              D
               Discriminator                                Event Formatting
                                                 TDC


    Analog Done w/ Discrete, More Digital Done w/ FPGA
            OpenPET System Architecture
        16 Analog
        Signals In         8 Boards In   8 Boards In    8 Boards In


                Detector     Support       Digital
                                                         Coincidence
                 Board        Board       Multiplexer
                                                               P
                               P
    Detectors




                                                          Host PC
            Data

           Control

   • Supports 256 Block Detectors (2048 With Multiplexers)
• PSB + 8 DPBs Makes Nice Test Stand (32 Block Detectors)
Detector 1: Conventional Block Detector
      12x12 array of 4x4x22 mm3 LSO crystals
            4 Hamamatsu R-9800 PMTs

      12%                                      11%




      12%                                      10%




          • Pre-Prototype Circuit Boards
  • Excellent Flood Map and Energy Resolution
                Detector 2: SiPM Array
  16x16 array                         Natural LSO Activity
3x3 mm2 SiPMs


                   Adapter Board

                     16x16 array
                          to
                      16 Row &
                     16 Column
                    Analog Sums


 3x3x20 mm3 &                           Pixel Intensity 
3x3x30 mm3 LSO                        Energy x Count Rate

  Same Electronics with Very Different Type of Detector
                                        Timing Resolution
                                      Test Pulse                                                      TOF Module Pair
                           2500                                                                    3000

                           2000                                                                    2500

         Counts per Bin




                                                                                  Counts per Bin
                                                                                                   2000
HPTDC                      1500

                           1000
                                                          56 ps fwhm                               1500
                                                                                                                                     286 ps fwhm

(CERN)                      500
                                                                                                   1000

                                                                                                    500

                              0                                                                       0
                              -200 -150 -100   -50   0    50    100   150   200                               -400   -200      0      200      400
                                                  Time (ps)                                                                 Time (ps)


                                  5                                                                       5
                           6 10                                                                    6 10
                                  5                                                                       5
                           5 10                                                                    5 10




                                                                                  Counts per Bin
          Counts per Bin




                                  5                                                                       5
                           4 10                                                                    4 10
                                  5                         90 ps fwhm                                    5                         255 ps fwhm
                           3 10                                                                    3 10
FPGA                       2 10
                                  5
                                                                                                   2 10
                                                                                                          5


                                  5                                                                       5
                           1 10                                                                    1 10

                              0                                                                       0
                              -200 -150 -100   -50    0    50   100   150   200                               -400   -200       0        200   400
                                                  Tim e (ps)                                                                Tim e (ps)



          • 16 Channel TDC in Cyclone II FPGA
  • Performance Good Enough for Time-of-Flight PET
                       Vision
Open Source
  •Hardware, Firmware, and Software
  •Schematics, Gerbers, BOM,…
Active User Community
  •Share Software and Expertise
  •Module, Calibration, DAQ, Display,…
Spring Fall, 2010
  •Detector & Support Boards Available
  •Work on Coincidence Board Begins
      http://OpenPET.LBL.gov

								
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