430.docx - UNL Computer Science _ Engineering by huanghengdong


									                                                                                      Computer Science & Engineering
                                                                                                       256 Avery Hall
                                                                                            Lincoln, NE 68588-0115
                                       Course Specification                                           (402) 472-2401

                                    Computer Architecture
Catalog Description:
430/830. Computer Architecture (3 cr) Prereq: CSCE 230, 231, 310, and Math 380 or EE 410 as co-requisite.
Credit not applicable toward graduate degree in computer science. Addresses the architecture of single-
processor (Von Neumann or SISD) computer systems with a quantitative approach. Students will learn the
advanced microprocessor design principles, implementation skills and evaluation methodologies on Pipelining,
Fundamental computer design, Instruction level parallelism, Cache/Memory Hierarchy, Memory systems and
I/O storage systems. Students will practice in design and implementation of a RISC pipeline microprocessor and
an application system.
Textbooks(s) and/or Other Required Materials:
   1. J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative
      Approach, 3rd edition, Morgan Kaufmann Publishers, Inc., San Mateo, California, 2002.
   2. D. A. Patterson and J. L. Hennessy, Computer Organization and Design: The Hardware/software
      Interface, 2nd Edition, Morgan Kaufman, 1997 (Optional).

Prerequisites by Topic:

   1. Mastery of: Boolean algebra, logic equations, binary numbers (including negatives), fixed-point binary
      arithmetic, hexadecimal notation, powers-of-2, logarithms, exponential numbers.
   2. Familiarity with: computer organization, including: logic gates & diagrams, processor organization &
      operation, memory devices & hierarchies, I/O devices & processes,
   3. Familiarity with: at least 1 assembler language, 1 high-level language, 1 graphical process
      representation (e.g. flow charts), basic data structures, basic logic design, simple datapaths
      implementation, basic pipelining principles, basic O.S. principles and functions.
   4. Exposure to: Basic probability (esp. calculating arithmetic and geometric mean values).

Course Objectives:

   1. Mastery of: the elements, structures, processes, design trade-offs, & performance issues of classical
      single-processor Computer Architectures, including:
          a. Scalar and superscalar processor architecture: their relationships to the hardware/software
              interface, quantitative approaches to the performance evaluation at different levels, competing
              design philosophies (e.g. five ISA classes, branch prediction schemes), the theory & practice of
              pipelining, superscalar, speculation, hands-on experience in the design and implementation of
              pipelined RISC based processor.
          b. n-level memory hierarchies (n>2): incl. Cache(s), main memory, virtual memory,
          c. I/O: disk drives, buses, redundant and inexpensive array, reliability/availability measurement.
   2. Mastery of: stochastic performance model derivation & evaluation, given standard stochastic & timing
      parameters (e.g. access times, CPI, hit ratios, memory stall times, I/O throughput).
Topics Covered:

   1. Processor Architecture Topics:
          a. Pipelining: concept, variations, performance, implementation and evaluation,
          b. Processor design issues: taxonomy of instruction set architectures, memory addressing, operands
             and operations in ISA, instructions for control flow, encoding ISA,
          c. Instruction-level parallelism (ILP): concepts, dynamic scheduling, dynamic hardware prediction,
             multiple issue processors, speculation.
   2. Memory System Topics:
          a. Hierarchical memory systems: concepts, motivation, performance, i) Cache: organization,
             management, write policies, performance improvement and evaluation, ii) Main memory:
             organization and operations, latency, cycle time, bandwidth, interleaving, performance, interface
             with cache, iii) Virtual memory: concepts, address translation, up-to 2-level translation tables,
          b. Technologies: (SRAM, DRAM, magnetic, optical), organization, operation, timing.
   3. I/O System Topics:
          a. Busses: architectures, operation, synch. & asynch. signaling conventions, arbitration, including
             extensive use of waveform diagrams,
          b. I/O devices & processes: programmed I/O, interrupt handling, DMA, I/O channels, bus-cycle
             arbitration, I/O throughput, raid architectures.

Relationship of Course to Program Objectives:
Contributes to Program Objective 1 through Program Outcome 2.c.

Contribution of Course to Meeting the Professional Component:
Contributes to Criterion 4.b through the study of Computer Architectures and design trade-offs.

Class/Laboratory Schedule:
Lecture: 45 hours = 3 hours/week for 15 weeks; Laboratory: 1 hour/week for 15 weeks.

Prepared by:
Jun Wang, Assistant Professor; Hong Jiang, Associate Professor; Witawas Srian-an, Assistant Professor.

                                                 2                                            03/01/12

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