# THE SEQUENTIAL LOGIC CIRCUITS by l62idC8

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```									THE
SEQUENTIAL LOGIC CIRCUITS

Outputs
Inputs          Combinational
Logic Circuit

Memory
Elements

Sequential Logic Circuit
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Outline
 Combinational Circuits vs. Sequential Circuits
 Flip-Flops
   RS-Flip Flop
   D-Flip-Flop
   JK-Flip Flop
   T-Flip Flop
 Registers
 Counters

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Combinational Circuits
 A circuit is combinational if it computes a function which depends
only on the current inputs applied to the circuit; for every input
set of values, there is a unique output set of values.

x1                                         z1
x2            Combinational                z2
Logic Circuit
xn                                         zm

Examples: Adder, Subtractor, Comparator, Coders,
Multiplexers & Demultiplexer
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Sequential Logic Circuits
 In a sequential Logic Circuit, the output values depend on the
inputs and MEMORY ELEMENTS where the previous outputs
values been stored

inputs                                                 outputs
Combinational
Logic Circuit

Memory
Elements

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Logic Circuits
 Combinational
x0       Combinational                    z0
x1                                        z1
xn       Logic Circuit                    zm

 Sequential Logic
outputs
inputs           Combinational
Logic Circuit
Memory
Elements

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Sequential Logic Circuits
 The memory elements used in clocked sequential logic
circuits are called flip-flops
 These circuits are binary cells capable of storing one bit of
information
 A flip-flop circuit has two inputs and two outputs(Normal
and Complemented )
 Input can be provided to a flip-flop in a variety of ways like(
SR, D, JK and T)

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ThE fLiP-fLoP
 "Flip-flop" is the common name given to two-state devices
which offer basic memory for Sequential Logic operations.
 Flip-flops are used for
• Digital data storage and
• Data transfer from or to the memory
 Flip-flop are commonly used in computer banks called
"registers" for the storage of binary numerical data.

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Basic Flip-Flop
 Two inputs (R and S) and two Output (Q and Q’)

NOR gate flip-flop                             NAND gate flip-flop
R            1                  Q                 S           1             Q

2                   Q’               R           2             Q’
S
S             R       Q          Q’                S           R       Q         Q’
1             0       1          0                 1           0       0         1
0             0       1          0                 1           1       0         1
0             1       0          1                 0           1       1         0
0             0       0          1                 1           1       1         0

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RS Flip-Flop

S                                   Q
>
R                                Q’

 Two Inputs:
 S(et) input
 R(eset) input and
CP( Clock Pulse) additional input to control when state is changing.

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S
RS fLiP-fLoP                                                       3       1             Q

CP

R     4       2             Q’
RS fLiP-fLoP Truth Table

S   R       Q(t) (Previous state)     Q(t+1){Current state}
0   0                0                           0
NO CHANGE
0   0                1                           1
0   1                0                           0                                 RESET
0   1                1                           0
1   0                0                           1
SET
1   0                1                           1
1   1                0                          i.d.                        RACE CONDITION
1   1                1                          i.d.

The Indetermined state in RS Flip-Flop is called Race-condition
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RS fLiP-fLoP (cont’d)
 Four States:
   No change:      S=0, R=0, CP=1
   Set state:      S=1, R=0, CP=1            (Q=1, Q’=0)
   Reset state:    S=0, R=1, CP=1            (Q=0, Q’=1)
   Indetermined:   S=1, R=1, CP=1            (Q=1, Q’=1)

1                                                            1
S                                    Q
1                 >
1                     R                                 Q’
0

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D Flip-Flop

D                 Q
>
Q’

 One Input:
 D: Set/Reset input
CP( Clock Pulse) additional input to control when
state is changing.

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D fLiP-fLoP
D       3       1                    Q
CP

2                    Q’
4

D Q(t) {Previous state}       Q(t+1) {Current state}
0     0                       0
RESET
0     1                       0
1     0                       1
SET
1     1                       1

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D fLiP-fLoP
 Two States:
 Set state:   D=1, CP=1
 Reset state: D=0, CP=1

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JK Flip-Flop

J                                   Q
>
K                              Q’

 Two Inputs:
 J: Set input
 K:Reset input
CP( Clock Pulse) additional input to control when state is
changing.

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JK Flip-Flop (cont’d)
K                            3                                1                       Q
CP

J                      4                                     2                   Q’

J   K        Qt {Previous state}            Q(t+1){Current state}
0   0                   0                                0
NO CHANGE
0   0                   1                                1
0   1                   0                                0                              RESET
0   1                   1                                0
1   0                   0                                1
SET
1   0                   1                                1
1   1                   0                                1                              toggle
1   1                   1                                0
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The Indetermined state in JK Flip-Flop is called toggle condition
JK fLiP-fLoP
 Four States:
   Set state:   J=1, K=0, CP=1
   Reset state: J=0, K=1, CP=1
   No change: J=0, K=0, CP=1
   Complement: J=1, K=1, CP=1 toggle condition

1                                  1
J                                 Q
1             >
K                             Q’
1                                  0

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T Flip-Flop

T                                Q
>
Q’

One input:
T: set/reset input
CP( Clock Pulse) additional input to control
when state is changing.

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T fLiP-fLoP
T               3                           1      Q
CP
4                            2      Q’

T Q(t){ Previous state}        Q(t+1){ current state}
0     0                        0
RESET
1     0                        1
0     1                        1
SET
1     1                        0

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T fLiP-fLoP
Two States:
 No Change: T=0, CP=1
 Complement: T=1, CP=1

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The fLiP-fLoP excitation tables
 Excitation table is a table that lists the required inputs for a
given change of states.
 In excitation table we find the inputs that cause that
specified transition.
 Excitation table are used in sequential circuit design

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The excitation tables
RS flip-flop                                JK flip-flop
Q(t)            Q(t+1)   S   R              Q(t)          Q(t+1)    J   K
0               0        0   X              0             0         0   X
0               1        1   0              0             1         1   X
1               0        0   1              1             0         X   1
1               1        X   0              1             1         X   0
D flip-flop                                 T flip-flop

Q(t)            Q(t+1)   D                    Q(t)         Q(t+1)   T
0               0        0                    0            0        0
0               1        1                    0            1        1
1               0        0                    1            0        1
1               1        1                    1            1        0
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Register
 A register is a group of flip flop with each flip flop storing 1
bit of information
   An n bit register consist of n flip flop and can store n bit
information
   A register can have gates as well perform some required
data processing or data transfer
   Transferring of new information into the register is called
   Transferring old information out of the register is called
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Example[4 bit register] using D flip flop

CP            1

0
1       I01                  I10           I21   I31
Clear
D                    D             D     D
0
1                    0             0
1     0
1
Q                    Q             Q     Q

A0                    A1           A2    A3

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Shift registers
 The register that can shift its content either to its right or left
is called shift register
 It is normally composed of chain of flip flops with the input
of one flip flop serve as the input to the next flip flop

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4 bit shift register
Serial input

0 1 0 1
D   Q       D           Q            D   Q   D   Q

CP            1

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4 bit shift register
Serial input

0 1 0          1
D   Q       D           Q            D   Q   D   Q

CP            1

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4 bit shift register
Serial input

0 1            0                    1
D   Q       D           Q            D   Q   D   Q

CP            1

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4 bit shift register
Serial input

0              1                   0                1
D   Q       D           Q            D   Q   D   Q

CP            1

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Counter design
 The sequential circuits( a register ) that goes through a
predetermined sequence of states upon the application of
input pulses is called counter.
   The input pulses are called counter pulses
   Counters are found in almost all the equipment containing
digital logic.
   Used for counting the number of occurrence of an event
   Also used for generating counting sequences to control
operations in digital systems

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Steps in counter design
 The word description of the circuit behavior.
 Obtain the state table from the given information
 Assign binary values to each state
 Determine the number of flip-flops to be used
 Choose the type of flip-flop to be sued
 Using Kmap obtain the circuit output functions and flip-flop
input functions
 Draw the logic diagram

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Example
Design a 3 bit binary counter using
T flip-flop

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Description

000
111                                001

110                                  010

101                                011
100
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The excitation table
Count Sequence                                   Flip-flop inputs
A2                A1            A0                 TA2            TA1                TA0
0                 0             0                  0              0                  1
0                 0             1                  0              1                  1
0                 1             0                  0              0                  1
0                 1             1                  1              1                  1
1                 0             0                  0              0                  1
1                 0             1                  0              1                  1
1                 1             0                  0              0                  1
1                 1             1                  1              1                  1

TA2=A2’A1A0+ A2A1A0
TA1=A2’A1’A0+ A2’A1A0+A2A1’A0+ A2A1A0

TA0=A2’A1’A0’ + A2’A1’A0+ A2’A1A0’ + A2’A1A0+ A2A1’A0’+ A2A1’A0 + A2A1A0’ + A2A1A0
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Expressions
TA2 = A2’A1A0 + A2A1A0                                        TA1 = A2’A1’A0+ A2’A1A0+A2A1’A0+ A2A1A0

TA2     A1’A0’      A1’A0   A1A0   A1AO’               TA1           A1’A0’   A1’A0    A1A0    A1AO’

A2’                         1                          A2’                    1        1
A2                          1                           A2                    1        1

TA2 = A1A0                                                                            TA1 = A0
TA1 = A2’A1’A0’ + A2’A1’A0+ A2’A1A0’ + A2’A1A0+ A2A1’A0’+ A2A1’A0 + A2A1A0’ + A2A1A0

TA0     A1’A0’      A1’A0   A1A0    A1AO’
A2’        1         1      1         1
A2         1         1      1         1
28-Feb-12
TA0 = 1
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Q   A0
COUNT PULSES
3 Bit Binary Counter

1          T

Q   A1

T

Q   A2

T

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111
000
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4 bit binary counter

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