ELEN 468 Advanced Logic Design Spring 2003

							                ELEN 468 Advanced Logic Design Fall 2008

                          Homework 1         Sept 22, Monday
1. Please discuss the advantages and disadvantages of the following IC design styles: (1)
custom design; (2) standard cell design; (3) FPGA and PLD.

2. For the following Verilog description of a 2-input NAND gate, the input signal is
switched from {A1,B1} = 11 to {A1,B1} = 10, please tell the maximum delay of the
output signal switching.

module myNAND(O, A1, B1);
     input A1, B1;
     output O;
     nand( O, A1, B1 );

       specify
              specparam
              T1 = 1:4:7;
              T2 = 2:3:5;

           (A1=>O) = ( T1, T2 );
           (B1=>O) = ( T2, T1 );
     endspecify
endmodule

3. Using Verilog predefined primitives, write a description of the circuit below.


 rst
                                                          q




                                                          qb
 set



4. Example 2.22 (page 50) of the textbook describes a 4-stage 8-bit pipeline of registers.
Please write Verilog code for a 5-stage 6-bit pipeline of registers.

5. Please write the binary equivalent of the following Verilog number.
    a. 8’h6
    b. 8’O35
    c. 8’bx