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FINITE STATE MACHINES

VIEWS: 25 PAGES: 31

									           FINITE STATE MACHINES - II
               STATE MINIMIZATION
                     PARTITIONING MINIMIZATION PROCEDURE
                     VENDING MACHINE EXAMPLE
               ANALYSIS OF SYNCHRONOUS SEQUENTIAL
                CIRCUITS
                     PROCEDURE
                     EXAMPLE
               ALGORITHMIC STATE MACHINES (ASM) CHARTS
               COMPLETE FSM DESIGN EXAMPLE
          PARALLEL-TO-SERIAL CONVERTER WITH PARITY
                  

          GENERATOR
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                         1
           FINITE STATE MACHINES - II
               STATE MINIMIZATION
                     PARTITIONING MINIMIZATION PROCEDURE

                            DEFINITION: Two states Si and Sj are said to be equivalent if and only
                             if for every input sequence , the same output sequence will be
                             produced regardless of whether Si or Sj are the initial states.
                            DEFINITION OF 1-SUCCESSOR : If the machine moves from state Si to
                             state Sv when input w = 1, then we say that Sv is a 1-successor of Si
                            DEFINITION OF 0-SUCCESSOR : If the machine moves from state Sj to
                             state Su when input w = 0, then we say that Su is a 0-successor of Si

                         IF STATES Si AND Sj ARE EQUIVALENT, THEN THEIR
                         CORRESPONDING K-SUCCESSORS (FOR ALL K) ARE ALSO
                         EQUIVALENT.
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                         2
           FINITE STATE MACHINES - II
               STATE MINIMIZATION

                     PARTITIONING MINIMIZATION PROCEDURE (CONTINUES)

                            DEFINITION: A PARTITION CONSISTS OF ONE OR MORE
                             BLOCKS, WHERE EACH BLOCK COMPRISES A SUBSET OF
                             STATES THAT MAY BE EQUIVALENT, BUT THE STATES IN A
                             GIVEN BLOCK ARE DEFINITELY NOT EQUVALENT TO THE
                             STATES IN THE OTHER BLOCK.




__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                         3
FINITE STATE MACHINES - II
   STATE MINIMIZATION
       PARTITIONING MINIMIZATION PROCEDURE (CONTINUES)
            PROCEDURE:
                 1) ALL STATES BELONG TO THE INITIAL PARTITION P1
                 2) P1 IS PARTITIONED IN BLOCKS SUCH THAT THE STATES IN
                     EACH BLOCK GENERATE THE SAME OUTPUT.
                 3) CONTINUE TO PERFORM NEW PARTITIONS BY TESTING
                     WHETHER THE K-SUCCESSORS OF THE STATES IN EACH
                     BLOCK ARE CONTAINED IN ONE BLOCK. THOSE STATES
                     WHOSE K-SUCCESSORS ARE IN DIFFERENT BLOCKS CANNOT
                     BE IN ONE BLOCK.
                 4) PRCEDURE ENDS WHEN A NEW PARTITION IS THE SAME AS
                     .THE PREVIOUS PARTITION



                                                                           4
   FINITE STATE MACHINES - II
         STATE MINIMIZATION
             PARTITIONING MINIMIZATION PROCEDURE (CONTINUES)
                  EXAMPLE: Consider the following state transition table

                                                    P1 = (ABCDEFG)
               Next state                           P2 = (ABD)(CEFG) Diff. Outputs.
Present                         Output     Because (CEFG) 0-successors are (FFEF) in
 state        w= 0     w= 1       z                             same block,
                                                    (CEFG) 1-successors are (ECDG)
  A            B         C         1                            in diff. block,
                                           F must be different from C, E and G
  B            D         F         1                P3 = (ABD)(CEG)(F)
  C            F         E         0                P4 = (AD)(B)(CEG)(F)
  D            B         G         1       Same process for (AD) and (CEG) gives
  E            F         C         0                P5 = (AD)(B)(CEG)(F)
                                                    P5 = P4
  F            E         D         0
  G            F         G         0
                                                                                   5
   FINITE STATE MACHINES - II
         STATE MINIMIZATION
             PARTITIONING MINIMIZATION PROCEDURE (CONTINUES)
               EXAMPLE (CONTINUES): MINIMAL STATE TRAMSITION TABLE
               ORIGINAL TABLE
                                       P4 = (AD)(B)(CEG)(F)
Present        Next state   Output          MINIMIZED TABLE
 state        w= 0   w= 1     z
                                     Present    Nextstate     Output
  A            B       C      1       state    w= 0   w= 1      z
  B            D       F      1
  C            F       E      0        A        B        C      1
  D            B       G      1        B        A        F      1
  E            F       C      0        C        F        C      0
  F            E       D      0        F        C        A      0
  G            F       G      0                                        6
           FINITE STATE MACHINES - II
               STATE MINIMIZATION
                     VENDING MACHINE EXAMPLE

                         Design an FSM that will dispense candy under the following
                         conditions:

                            1.-      The machine accepts nickels and dimes
                            2.-      15 cents releases a candy from the machine
                            3.-      If 20 cents is deposited, the machine will not return the
                                      change, but it credit the buyer with 5 cents and wait for
                                      the buyer to make a second purchase

__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                         7
           FINITE STATE MACHINES - II
               STATE MINIMIZATION
                      VENDING MACHINE EXAMPLE (Continues)
               Clock

            sense
                N


            sense
                D


                 N


                 D


                                                 (a) Timing diagram
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                         8
           FINITE STATE MACHINES - II
               STATE MINIMIZATION
                      VENDING MACHINE EXAMPLE (Continues)


                                                                                          N
                      sense
                          N          D    Q             D    Q

                       Clock              Q                  Q



                                         (b) Circuit that generates N



__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                         9
           FINITE STATE MACHINES - II
            STATE MINIMIZATION: VENDING MACHINE EXAMPLE (Continues)
                                                   DN
                                                               Reset
       DN
               DN                                 S10                                DN
                           DN                                               DN
                                              D           N
                S41            S20                            S30      D     S71
                          N
                                     D                                 N
                                                    DN
                                 S51                              S60         DN         DN

                                                                N        D

                     S81         S91
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                         10
           FINITE STATE MACHINES - II
               STATE MINIMIZATION
                     VENDING MACHINE EXAMPLE (Continues)
Present     Next state Output
 state DN =00 01 10 11  z                                         P1 = (S1, S2, S3, S4, S5, S6, S7, S8, S9)
                                                                 P2 = (S1, S2, S3, S6)(S4, S5, S7, S8, S9)
 S1      S1 S3 S2 –    0                                         P3 = (S1)(S3)(S2, S6)(S4, S5, S7, S8, S9)
 S2      S2 S4 S5 –    0                                         P4 = (S1)(S3)(S2, S6)(S4, S7, S8)(S5,S9)
 S3      S3 S6 S7 –    0                                         P5 = (S1)(S3)(S2, S6)(S4, S7, S8)(S5,S9)
 S4      S1 – – –      1
 S5      S3 – – –      1
 S6      S6 S8 S9 –    0
 S7      S1 – – –      1
 S8      S1 – – –      1
 S9      S3 – – –      1
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                         11
        FINITE STATE MACHINES - II
STATE MINIMIZATION: VENDING MACHINE EXAMPLE (Continues)
MINIMIZED STATE TRANSITION TABLE AND DIAGRAM    DN


                                                    S10
 Present     Next state Output
  state DN =00 01 10 11  z                              N
                                               DN
   S1       S1   S3 S2   –   0                      S30
                         –               D
   S2       S2   S4 S5       0
   S3       S3   S2 S4   –   0    DN                N           DN
   S4       S1   – –     –   1                              D
   S5       S3   – –     –   1            DN        S20        S51

                                                    N
                                                                 D
                                                    S41
                                                                         12
         FINITE STATE MACHINES - II
       STATE MINIMIZATION: VENDING MACHINE EXAMPLE (Continues)
MINIMIZED STATE TRANSITION DIAGRAM: Moore-type versus Mealy-type
                       DN                                  DN0
MOORE-TYPE                                                                 MEALY_TYPE
                       S10                                 S1

                           N                         N0           D1
                  DN                               DN0
                       S30                N1             S3            D0
           D
    DN                 N           DN
                                                     N0           D1
                       S20   D    S51
             DN
                                                             S2
                       N
                                    D
                                                            DN0                   13
                       S41
           FINITE STATE MACHINES - II
               ANALYSIS OF SYNCHRONOUS SEQUENTIAL
                CIRCUITS
                     PROCEDURE: is the reverse of the synthesis process.
                            1.- OUTPUTS OF FLIP-FLOPS ARE THE INTERNAL STATES.
                            2.- INPUT EQUATIONS TO FLIP-FLOPS DETERMINE NEXT INTERNAL
                                 STATE.
                            3.- EXCITATION TABLE IS CONSTRUCTED FROM THESE INPUT
                                 EQUATIONS TO FLIP-FLOPS. OUTPUT EQUATIONS ARE PRODUCED.
                            4.- THE STATE-ASSIGNED TABLE IS PRODUCED FROM THE EXCITATION TABLE
                            5.- THE STATE-TRANSITION TABLE IS PRODUCED BY ASSIGNING A STATE
                                 IDENTIFICATION LETTER TO EACH ASSIGNED STATE.
                            6.- THE STATE-TRANSITION DIAGRAM IS PRODUCED FROM THE STATE-
                                 TRANSITION TABLE.

__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                         14
               FINITE STATE MACHINES - II
                       ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
                          EXAMPLE: ANALYZE THE FOLLOWING CIRCUIT
                                                       Exitation equations: DY1 = w !y1 + w y2
                            Y1           y1
                                                                              DY2 = w y1 + w y2
                                                                                z = y1 y2
                                 D   Q
                                                       z

                                     Q
w                                                        Next state equations:
                                                                  Y1 = DY1 = w !y1 + w y2
                            Y2           y2
                                 D   Q
                                                                  Y2 = DY2 = w y1 + w y2
                Clock                Q


               Resetn




    __________________________________________________
    ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
    Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                             15
           FINITE STATE MACHINES - II
               ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
                EXAMPLE (Continues)
                                                                                       Next State
Exitation equations:                                                  Present
                                                                                                            Output
                    DY1 = w !y1 + wy2                                  state
                                                                                    w= 0        w= 1
                    DY2= w y1 + w y2                                     2 1
                                                                        y y           2 1          2 1          z
                       z = y1 y2                                                     YY          YY
Next state equations:                                                    00           00          01            0
                 Y1 = DY1 = w !y1 + w y2                                 01           00          10            0
                  Y2 = DY2 = w y1 + w y2                                 10           00          11            0
                                                                         11           00          11            1


                                                                               (a) State-assigned table
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                         16
           FINITE STATE MACHINES - II
                ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
                 EXAMPLE (Continues)
                         Next State
        Present                                                     Present          Next state           Output
                                              Output
         state                                                       state
                      w= 0        w= 1                                                                        z
           2 1
                                                  z                               w= 0        w= 1
          y y           2 1          2 1                                A            A           B            0
                      YY           YY
           00           00          01            0                     B            A           C            0
           01           00          10            0                     C            A           D            0
           10           00          11            0                     D            A           D            1
           11           00          11            1

                                                                                  (b) State table
__________________________________________________
       (a) State-assigned table
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                         17
           FINITE STATE MACHINES - II
               ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
                ANOTHER EXAMPLE: Analyze the following circuit
                                                               J1                y1
       w                                                             J     Q
                                                                                                           z
                                                                    K      Q
                                                              K1




                                                               J2                y2
                                                                     J     Q
                                             Clock
                                                                    K      Q
                                                              K2
__________________________________________________
                   Resetn
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                         18
               FINITE STATE MACHINES - II
                   ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
                    ANOTHER EXAMPLE (Continues)
w
                               J1
                                  J Q
                                      y1          Excitation Equations
                                                z
                                                     J1 = w
                                  K Q
                               K1                    K1 = !w + !y2
                                                     J2 = w y1
                                                     K2 = !w
                                          J2
                                               J    Q
                                                        y2
                                                                                      z = y1 y2
                             Clock
                                               K Q
                                          K2

    __________________________________________________
              Resetn
    ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
    Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                             19
           FINITE STATE MACHINES - II
               ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
                ANOTHER EXAMPLE (Continues)
                Excitation Equations
                J1 = w
                K1 = !w + !y2     Present        Flip-flop inputs
                J2 = w y1          state      w= 0            w= 1                                            Output
                K2 = !w            y2 y1                                                                         z
                                          J 2K 2 J 1K 1 J 2K 2 J 1K 1
                z = y1 y 2
                    00    01   01   00    11    0
                    01    01   01   10    11    0
                    10    01   01   00    10    0
                    11    01   01   10    10    1
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                         20
                FINITE STATE MACHINES - II
    ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS ANOTHER EXAMPLE
     (Continues)
                EXCITATION TABLE                 STATE-ASSIGNED TABLE

    Present                Flip-flop inputs
                                                                                                Next State
                                                                Output         Present
     state           w= 0                    w= 1                                                                     Output
                                                                                state
     y2y1                                                          z                         w= 0        w= 1
                J 2K 2     J 1K 1      J 2K 2       J 1K 1                         2 1
                                                                                                                         z
                                                                                 y y            2 1         2 1
                                                                                              YY          YY
     00   01   01   00    11   0      00   00   01    0
     01   01   01   10    11   0      01   00   10    0
     10   01   01   00    10   0      10   00   11    0
     11   01   01   10    10   1      11   00   11    1
     __________________________________________________
     ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
     Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                              21
           FINITE STATE MACHINES - II
                ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
                 EXAMPLE (Continues)
                         Next State
        Present                                                     Present          Next state           Output
                                              Output
         state                                                       state
                      w= 0        w= 1                                                                        z
           2 1
                                                  z                               w= 0        w= 1
          y y           2 1          2 1                                A            A           B            0
                      YY           YY
           00           00          01            0                     B            A           C            0
           01           00          10            0                     C            A           D            0
           10           00          11            0                     D            A           D            1
           11           00          11            1

                                                                                  (b) State table
__________________________________________________
       (a) State-assigned table
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                         22
           FINITE STATE MACHINES - II
               ALGORITHMIC STATE MACHINES (ASM) CHARTS
                  DEFINITION: An ASM is a type of flowchart that can be used to represent
                   the state transitions and generated outputs for LARGE FSMs.
                  THREE TYPES OF ELEMENTS:
                             STATE BOX, DECISION BOX, CONDITIONAL OUTPUT BOX.
  State name


         Output signals
                                0 (False)           Condition              1 (True)           Conditional outputs
           or actions
                                                    expression                              or actions (Mealy type)
         (Moore type)




                                                                                           (c) Conditional output box
          (a) State box
__________________________________________________
                                                 (b) Decision box
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                         23
           FINITE STATE MACHINES - II
               ALGORITHMIC STATE MACHINES (ASM) CHARTS (Continues)
                                                          Reset
               Example: Moore-type
                 Reset
                                                                                   A
                                w=1
w=0             A z = 0                     B z = 0
                                                                               0       w
                                w=0                                                         1
                  w=0                        w=1                                   B


                              C z = 1                                        0       w
                                                                                            1

                                w=1                                                C
                                                                                        z

                                         1                                     0
__________________________________________________
                                     w
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                         24
               FINITE STATE MACHINES - II
                  ALGORITHMIC STATE MACHINES (ASM) CHARTS (Continues)
                     EXAMPLE (Mealy-type)              Reset




                                                                                        A

                    Reset
                         w = 1 z = 0
                                                                                    0
                                                                                            w
w = 0z = 0          A                     B            w = 1 z = 1                          1



                            w = 0 z = 0                                               B

                                                                                                                z




                                                                                    0               1
                                                                                            w


   __________________________________________________
   ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
   Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                            25
                FINITE STATE MACHINES - II
                ALGORITHMIC STATE MACHINES (ASM) CHARTS (Continues)
ANOTHER EXAMPLE (ARBITER MOORE-TYPE FSM): FSM THAT CONTROLS THE ACCESS BY VARIOUS DEVICES TO A SHARED
RESOURCE IN A GIVEN SYSTEM. ONLY ONE DEVICE CAN USE THE RESOURCE AT A TIME.
            Reset
                                                                      Reset               r 1r 2 r 3

     Idle                                                                          Idle

                                                                              r1          r1
                     1
                r1                                                            gnt1 g1 = 1
            0              gnt1                 1
                                                        0
                                  g1             r1                   r2                  r1           r 1r 2
                     1
                r2                                                            gnt2 g2 = 1
            0              gnt2                 1
                                                        0
                                  g2             r2              r3                       r2                r 1r 2 r 3
      0              1
                r3
                                                                              gnt3 g3 = 1
                           gnt3                 1
                                                        0
                                  g3             r3                                       r3
                                                                                                                26
           FINITE STATE MACHINES - II
               COMPLETE FSM DESIGN EXAMPLE
                  PARALLEL-TO-SERIAL CONVERTER WITH PARITY GENERATOR

                     Word description

                            Design a digital systems that will convert an 8-bit parallel
                             message, (b7 , b6 , b5 , b4 , b3 , b2 , b1 , b0), composed
                             of 7-bit ASCII character plus an initially set to 0 parity
                             bit, into an 8-bit serial message with the correct parity
                             bit set into bit b7 .


__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                         27
           FINITE STATE MACHINES - II
               COMPLETE FSM DESIGN EXAMPLE
                  PARALLEL-TO-SERIAL CONVERTER WITH PARITY GENERATOR
                   BLOCK DIAGRAM (Data Path and Control Unit)




__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                         28
           FINITE STATE MACHINES - II
               COMPLETE FSM DESIGN EXAMPLE
                  PARALLEL-TO-SERIAL CONVERTER WITH PARITY GENERATOR
                   STATE TRANSITION TABLE




__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                         29
           FINITE STATE MACHINES - II
               COMPLETE FSM DESIGN EXAMPLE
                  PARALLEL-TO-SERIAL CONVERTER WITH PARITY GENERATOR
                   STATE-ASSIGNED TABLE




                     CHOICE OF FLIP-FLOPS AND EXCITATION EQUATION
                                       Dy = Y = w  y
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                         30
           FINITE STATE MACHINES - II
               COMPLETE FSM DESIGN EXAMPLE
                  PARALLEL-TO-SERIAL CONVERTER WITH PARITY GENERATOR
                   CIRCUIT




__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.
                                                                                                                         31

								
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