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ECSE 323 Lab Report 4

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ECSE 323 Lab Report 4 Powered By Docstoc
					McGill University




ECSE 323: Lab Report 4
The Square Wave Generator Circuit
Group 21:
Tejas Deshpande (260264258)
Vinod Sridharan (260256868)




                                    Winter
                                     2009
Table of Contents
Introduction ............................................................................................................................................................................... 3
Design ........................................................................................................................................................................................... 3
Implementation ........................................................................................................................................................................ 3
    The MIF file generation .................................................................................................................................................... 3
    The VHDL code .................................................................................................................................................................... 3
Test bed circuit ......................................................................................................................................................................... 6
Simulation................................................................................................................................................................................... 6




List of Figures

Figure 1: The Block Diagram Schematic of Square Wave Generator circuit ................................................... 4
Figure 2: Square Wave Generator.......................................................................... Error! Bookmark not defined.5
Figure 3: Vector Waveform ................................................................................................................................................. 7
Figure 4: Compilation Report .................................................................................. Error! Bookmark not defined.7
Figure 5: Timing Analyzer Summary.................................................................... Error! Bookmark not defined.7
Introduction

The circuit was supposed to generate a square wave with amplitude equal to the volume input and
frequency determined by the note number and the octave inputs.


Design

The square wave output was represented by a 24 bit signed number. The circuit accepted the note
number as a 4 bit input. The note number would represent a number between 0 and 11. The rest of
the values were undefined. The octave input was represented as 3 bit input and volume as a 23 bit
unsigned value.


Implementation

The MIF file generation

To implement the square wave generator circuit using a Look Up Table (LUT), we used the LPM
library in Quartus software package. The ROM module required the use of a MIF file with a
particular syntax. There were two ways of making the MIF file, the brute force way or automating
the process by coding it. We used MATLAB code to generate the entries of the LUT due to the
simplicity of the built-in functions. Once generated, we added the header and footer data to the MIF
file and proceeded to generate out VHDL code.

The VHDL code

Pin Name         Data         Mode     Type          Description
                 Width
                 (bits)
                 1            IN       STD Logic     The clock input for the different sub modules
                 23           IN       Unsigned      The value of the square wave amplitude
                 4            IN       STD Logic     The input to the exponentiator module
                 3            IN       STD Logic     The input to the barrel shifter module
                 24           OUT      Signed        The square wave resulting from the input
                                                     parameters
Figure 1: The Block Diagram Schematic of Square Wave Generator circuit

The design of this circuit involved combining the frequency and the amplitude component to
generate a square wave. The frequency component was determined by the “octave” and
“note number” inputs. A one bit square wave with the desired frequency was generated using the
frequency divider module used in lab 3. The implementation of the circuit can be seen as follows in
Figure 2. Then depending on whether the value of the one bit square wave was 1 or 0, the unsigned
volume input signal was transferred directly to the 24 bit signed output or negated respectively.
                                                                                                                                                                                                           Equal0
                                                                                                                                                                                                A[31..0]


                                                                                                       freq~[23..0]                                                          32' h00000000 --
                                                                                                                                                                                                B[31..0]
                                                                                                                                                                                                            =       freq~[47..24]

                                                                                                               SEL                                                                                         EQUAL            SEL
                                                                                                                                                                                                                                         freq[23..0]
                                 2' h3 --
                                                       Add0                                                                                                                                                         DATAA                     PRE
    volume[22..0]                           A[25..0]                                 1' h0 --
                                                                                                       DATAA                                                                                                                      OUT0    D         Q   square[23..0]
                                                                                                                      OUT0                                                                                          DATAB
                                 1' h1 --
                                            B[25..0]
                                                         +                                             DATAB                                count~[31..0]
                         26' h0000001 --                                                                                                                                                                                                  ENA
                                                                                                                                                                                                                        MUX21                 CLR
                                                       ADDER
                                                                                                                                                    SEL          count[31..0]
                                                                                                              MUX21                         DATAA
                                                                                                                                                                       PRE
                                                                                                                                                          OUT0     D          Q
                                                                                                                                            DATAB
                                                                                                                             14' h0000 --

                                                       LessThan0                                                                                                   ENA
                                            A[23..0]                                                                                                                   CLR
                          23' h000000 --                                                                                                        MUX21
                                 1' h0 --
                                            B[23..0]
                                                         <
                                                   LESS_THAN



                                                       Add1
                                            A[32..0]
                                 1' h1 --
                     33' h1FFFFFFFD --
                                            B[32..0]
                                                         +
                                                       ADDER

                                                           LPM_ROM:crc_table
                                                                                                           ShiftRight0
               clk                                     inclock
                                                                                                A[18..0]
                                                       outclock           q[18..0]

note_number[3..0]                                      address[3..0]
                                                                                                COUNT[2..0]
                                                                                                           >>
                                                                                                      RIGHT_SHIFT




      octave[2..0]
            reset



   Figure 2: The Square Wave Generator Circuit
             Test bed circuit

             To test the square wave generator, we were required to connect our square wave to the audio
             codec chip. To do this, we needed two additional stages of processing to be done in order to
             interface with the audio codec chip. This was done by the Decimator and the Audio Interface files.
             By component instantiation, we connected the output of the square wave generator to the
             decimator and the output of the decimator to the Audio Interface module. Through that, we
             connected to the codec chip. The test bed was as follows:



                                                                                                                            g21_audio_interface:myAudioInterface

                                                                                                                                                       AUD_BCLK     AUD_BCLK
        audio_init                                                                                                           INIT
                                                                                                                                                     AUD_DACDAT     AUD_DACDAT
                                           g21_square_wave:mySquare                                                     1    W_EN
                                                                                    g21_decimator:myDecimator                                       AUD_DACLRCK     AUD_DACLRCK
                                                                                                                             clk
              clk                    clk                                                                                                               AUD_MCLK     AUD_MCLK
                                                                              clk                                            rst
            reset                    reset                                                                                                              I2C_SCLK    I2C_SCLK
                                                                              rst                      SR48KHz[23..0]        LDATA[23..0]
note_number[3..0]                    note_number[3..0]                                                                                                  I2C_SDAT    I2C_SDAT
                                                              square[23..0]   SR24MHz[23..0]                                 RDATA[23..0]
      octave[2..0]                   octave[2..0]                                                                                                     pulse_48KHz   pulse_48KHz
     volume[2..0]
                                     volume[22..0]
                     20' hFFFFF --




             Figure 3: The Square Wave Test Bed

             The above figure clearly labels the inputs and outputs. The Clock input was connected to the 24
             MHz clock. The Reset and Audio Init were connected to push buttons and the rest of the
             components i.e. note_number, octave and volume were connected to the slide switches. Only the 3
             MSBs of the volume were connected to the slide switches to get observe a significant volume.


             Simulation

             We needed to test the circuit for 4 values of note_number and octave each. To minimize the total
             simulation time, the maximum 4 values of the note_number and octave were chosen for the
             simulation. The counter was reset every time for a new combination of inputs. Since the volume
             input was only used in the multiplication step, it was least likely to have bugs. As a result it was not
             necessary to vary the volume input to test the circuit. The simulation output can be seen in Figure 3.
             The simulation outputs were as expected.
Figure 4: Vector Waveform

The compilation report is as follows:




Figure 5: The Compilation Report

The square wave generator circuit took 5% logic elements to synthesize and required 812 registers
to implement.

The Timing Analyzer Summary is as follows:
Figure 6: The Timing Analyzer Summary

From the above Timing Analyzer summary it can be seen that the Maximum clock frequency that
the circuit can operate is:


                                                                   .
                                          .       .       .

				
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