EW-MOVPE XIII, Ulm, 2009 C.06 GaAs-growth on porous silicon 1 2 1 1 1 M. Wiesner , E. A. Angelopoulos , R. Roßbach , M. Jetter and P. Michler 1 Institut für Halbleiteroptik und Funktionelle Grenzflächen, Universität Stuttgart, Allmandring 3, 70569 Stuttgart, Germany 2 Institut für Mikroelektronik Stuttgart (IMS CHIPS), Allmandring 30a, 70569 Stuttgart, Germany Abstract We present investigations of porous silicon as a compliant substrate for gallium arsenide-silicon heteroepitaxy. GaAs layers were grown on samples consisting of porous Si layers with different porosities and layer thicknesses formed on the surface of bulk Si substrates. The resulting structures were investigated by high resolution X-ray diffraction, scanning electron microscopy and photoluminescence measurements. An improvement of the crystal quality of GaAs layers grown on specially treated porous Si substrates compared to layers grown directly on bulk Si substrates could be shown. Introduction Silicon (Si) is the most commonly used basic material in microelectronics. Outstanding features of Si substrates are small mass, good thermal conductivity, large wafer diameter and, most of all, low cost. Disadvantageous however is silicon’s indirect bandgap. For this reason, III-V compounds, primarily gallium arsenide (GaAs), serve as a basic material for optoelectronic devices. Monolithic integration of both material systems with the prospect of economically fabricating integrated circuits is highly desirable. Major problems however are the 4 % lattice mismatch between Si and GaAs, leading to a large density of misfit dislocations, and also the big difference in thermal expansion coefficients, which causes crack formation due to large post-growth tensile stress in the GaAs layer. In the last 20 years many efforts have been made to overcome these difficulties, such as thermal cycle annealing, implementation of a strained layer superlattice, GaAs overgrowth on GaAs bonded to Si, growth through buffer layers and use of compliant substrates. We follow the latter approach by using porous silicon (PSi) for the realization of compliant substrates. PSi layers are considered to be mechanically flexible providing the ability to relax the stress resulting from lattice mismatch and thermal expansion coefficients by straining the “softer” porous structure. Aim of this study was to find the parameters of PSi layers best suitable for GaAs/Si-heteroepitaxy. For this purpose we characterized PSi layers with different values of thickness and porosity using high resolution X-ray diffraction (HRXRD) measurements. GaAs layers of different thicknesses were then grown on PSi samples by metal-organic vapor-phase epitaxy (MOVPE). Experimental PSi layers were fabricated on 6-inch p-type (100) Si wafers by anodization in an electrochemical etching cell containing an electrolytic solution of 50% w/w hydrofluoric acid (HF) and isopropanol in a 3:1 volume ratio, the latter used as a wetting agent. The thickness of the layers was measured using scanning electron microscopy (SEM) and the porosity could then be calculated gravimetrically . Adjustment of thickness and porosity was carried out by varying the process time, anodization current and wafer doping level, in such a way that resulted in homogeneous PSi layers with well defined properties. After the PSi formation and a rinse-dry procedure, half-wafers were subjected to a 5 min thermal annealing step at 1100°C in hydrogen atmosphere. During this step sintering of the porous material is observed with atoms recrystallizing in an energetically favorable structure of crystalline Si incorporating spherical vacuum cavities. Both the as-etched and the annealed PSi/Si samples having PSi thicknesses ranging from 0.5 μm to 10 μm and porosities from 20% to 60% were used as substrates for GaAs growth. Prior to epitaxy, the substrates were dipped in HF to remove the native oxide. The growth of GaAs was carried out by MOVPE in an AIX-200 horizontal reactor setup at low pressure of 100 mbar. The source materials were trimethylgallium (TMGa) and arsine (AsH3). The samples were characterized by HRXRD, SEM, atomic force microscopy (AFM) and photoluminescence (PL). PL spectra were recorded at 4 K using 514.5 nm Ar-ion laser as an excitation source. EW-MOVPE XIII, Ulm, 2009 C.06 Results Prior to the core GaAs-growth experiments, compliant 004-ReflectionPorous Si 2µm substrate samples with different combinations of PSi layer Porosity 60% Normalized log intensity (arb. u.) thickness and porosity were subjected to HRXRD measurements FWHM 35" in order to evaluate the crystalline properties of PSi. Figure 1 ∆ω= 352" Substrate -3 FWHM 18'' compares the rocking curve of the 004-reflection from as-etched ∆a/a = 2.4*10 samples with a PSi layer thickness of 2 µm and different degree of porosity. For 20% porosity, the relative change of the lattice constant with respect to the Si substrate is ∆a/a=2.2*10 . An -4 increase by one order of magnitude is observed for the sample Porosity 30% with 60% porosity. The Bragg peak originating from the PSi layer FWHM 24" Substrate shows a full width half maximum (FWHM) which is comparable ∆ω= 50" FWHM 22'' to the one from the bulk Si substrate, thus demonstrating the -4 ∆a/a = 3.4*10 excellent crystalline quality of the top porous layer and the suitability of the samples for GaAs epitaxial overgrowth. The initial nucleation layer plays an important role in the Porosity 20% crystalline quality of the final GaAs layer. GaAs growth on Si FWHM 16" ∆ω= 32" Substrate starts with formation of 3D islands (Volmer-Weber growth) , FWHM 15" -4 turning into a quasi-2D growth mechanism (Frank-van der ∆a/a = 2.2*10 Merve). For optimal growth results, these islands should be small and grow at a high density, preventing them from -400 -200 0 200 becoming defective even before they coalesce. In order to find the best PSi parameters for the nucleation, 20 nm GaAs were ∆ω(arcsec) grown on different substrates and analyzed by AFM. The growth Figure 1 Rocking curves from as-etched temperature was set to 400°C, as is typically done for nucleation PSi/Si samples for different values of layers. AFM results show no clear tendency which porosity and porosity porous layer thickness might be favorable. However there is a significant difference between layers grown on annealed and as-etched compliant substrates, as shown in figure 2 for a sample with a PSi layer with 20% porosity and a thickness of 2 µm. The GaAs nucleation layer grown on the annealed substrate shows a much smoother surface with a roughness of 0.97 nm, in contrast to 2.64 nm on the as-etched substrate. (a) (b) Figure 2 AFM pictures of a 20 nm GaAs nucleation layer on porous Silicon (a) as-etched (b) annealed. EW-MOVPE XIII, Ulm, 2009 C.06 The most widely used technique for epitaxy of GaAs on Si is the so-called two-step growth . This method implies growth of a nucleation layer at low temperature (400°C), followed by the main layer at temperatures of about 600-750°C. We chose a thickness for the nucleation layer of 20 nm and then grew 1 µm GaAs on different compliant substrate samples, both annealed and as-etched. SEM pictures of these structures show a similar result as the investigation of the nucleation. While GaAs layers on the as-etched samples do not show an improvement in crystal quality compared to layers grown on bare Si substrates (w/o porous layer), layers on annealed samples clearly exhibit less defects. This result is confirmed by HRXRD. The rocking curve FWHM of GaAs on an annealed compliant substrate shows a decrease of about 40’’ compared to that on an as-etched, for all porosities and PSi layer thicknesses. Best FWHM (267’’) was achieved for the substrate with PSi 10 µm /20% porosity. For bulk Si, the best value reported for 1 µm GaAs on (100) oriented substrate (4.5° towards <001>) is 189’’ . PL investigations also showed a significantly higher intensity on annealed substrates. For all samples the PL FWHM was in a range between 30 and 40 meV and did not show any trend in relation to PSi thickness or porosity. Furthermore, the quality of samples grown by thermal cyclic growth (TCG)  was investigated. According to this method, first a 1.8 µm thick GaAs layer was grown similarly to the two-step growth method described above. Next, a temperature cycle step was performed, during which thin GaAs films were deposited at alternating low (400°C) and standard (700°C) temperatures. Each low temperature step was followed by an annealing sequence at 790°C. The idea of this cyclic growth is to introduce dislocations during the low temperature growth which may interact with existing dislocations in the layer below during the subsequent annealing steps. After this cyclic growth a thick GaAs layer (1.6 µm) was deposited, resulting in a total thickness of the sample of 3.6 µm. These samples show a substantial decrease in (004)-GaAs-FWHM (arcsec) rocking curve FWHM of up to 70’’ compared to 360 samples grown by two-step method (Fig. 3). This is Porosity 20 % partly also a consequence of the increased thickness 340 as-etched annealed of the GaAs layers on the TCG samples, which 320 decreases the dislocation density. Again, layers grown on annealed substrates show better results. 300 1 µm Two-step growth Best FWHM (218’’) was achieved for a PSi thickness 280 of 10 µm and 20% porosity. Figure 4 shows SEM pictures of this sample and, for comparison, of GaAs 260 grown on bulk Si using the same recipe. Looking at 3.6 µm TCG 240 the cross section it can be seen that there are considerable fewer defects in the layer grown on the 220 porous sample. Furthermore, the surface is much bulk Si 2µm 10µm smoother and shows broad coalescent areas. PL Thickness of porous Si layer (µm) intensity of TCG samples is generally increased, while PL FWHM show a slight decrease of about 5 Figure 3 Comparison of rocking curve FWHM for meV, compared to two-step growth results. 1µm two-step growth and 3.6 µm thermal cyclic For a detailed analysis of the dislocation density, growth samples have to be investigated by transmission electron microscopy. EW-MOVPE XIII, Ulm, 2009 C.06 Figure 4 SEM pictures of GaAs layers grown by thermal cyclic growth on bulk Si (upper row) and on porous Si (lower row). Shown is the cross section (left) and the surface (right), respectively. Conclusion / Outlook Compliant substrates consisting of porous silicon surface layers were investigated as substrate material for GaAs epitaxy. GaAs layers were deposited by two-step growth as well as by thermal cyclic growth. It could be demonstrated that GaAs layers grown on annealed porous layers show better crystal quality and fewer defects than layers grown on bulk Si. Rocking curve FWHM for a 3.6 µm thick GaAs layer down to 218’’ could be reached. Nucleation and growth parameters will be further optimized. In addition, samples with an AlGaAs double- heterostructure on top of the GaAs layer will be grown to perform time-resolved PL measurements, which give a deeper insight on structural defects. Acknowledgement The authors would like to thank E. Kohler for technical assistance with the MOVPE system, A. Fuoss for sample preparation and S. Ferwana for his help during the fabrication of the PSi layers. References  E. A. Angelopoulos, S. Ferwana, M. Zimmermann, E. Penteker, J. N. Burghartz, in Proc. 11th Annu. Work. SAFE, pp. 445-448, The Netherlands, 2008.  D. K. Biegelsen, F. A. Ponce, A. J. Smith, J. C. Tramontana, J. Appl. Phys. 61 (1987) 1856.  M. Akijama, Y. Kawarada, K. Kaminishi, J. Cryst. Growth. 68 (1984) 21.  D. A. Vinokurov at al., Sov. Phys. Semicond. 25 (1991) 617.  R. Dieter, “Defekte bei der Heteroepitaxie von Galliumarsenid auf Sillizium”, Dissertation, Universität Stuttgart (Juni 1993).
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