Maria S. Joseph
1025 University Avenue, Apt #126, Sacramento CA - 95825 (916) 996-4499 firstname.lastname@example.org
To obtain a position in VLSI/ASIC circuits Design or Validation, Product development, Component design or Computer architecture
Master of Science, Electrical and Electronics Engineering, CSU, Sacramento Expected December2009 3.565/4.0
Bachelor of Engineering, Electronics and Communication Engineering, Anna University, India May 2007 3.6/4.0
RELATED COURSE WORK:
Advanced Logic Design CMOS and VLSI Design Micro Computer System Design I
Advanced Timing Analysis Digital Electronics Analog and Mixed Signal IC Design
Microwave Devices & Circuits Advanced VLSI Design-For-Test I Microprocessor and its Applications
Computer Communication Networks Wireless Communication Systems Advanced VLSI Design-For-Test II *(in progress)
Hardware Description Languages: Verilog, VHDL
Scripting/ Programming Languages: TCL, C, Perl, Unix
Simulation Tools: Xilinx ISE, ModelSim
Tools/Packages: Synopsys VCS, L-EDIT, PSPICE, Mentor Graphics* (Analog circuit dsgn tool), MS Office
Timing Analysis Tool: Design Vision, Primetime, Design Analyzer (OS: Centos, Linux)
Platforms/Environments: Windows (95/98/2K, XP, Vista, 7), Linux, Centos
VLSI (Tools & flows): IC Manufacturing flow; DFT(SCAN tests); ATPG(FastScan); BIST; JTAG; TAP
Some knowledge on failure analysis: LADA, IERM, FIB, Pico probing
Organization and Awards: Coordinator, team player, quick learner. Awardee of the General Engg Scholarship(CSUS)
Advanced Logic Design:
Projects on design of hierarchical circuits using Verilog coding: Designed an interface of SRAM with FPGA board to perform read/write
cycle operation. Designed an interface of programmed FLASH with SRAM to read the data of FLASH on logic analyzer. Designed an
interface of ADC with FPGA board and the analog convert digital data was read on the LCD. Designed sequence detector, calculator,
keypad program using Verilog, VHDL. All designs with 97% output on an average.
Advanced Timing Analysis:
Projects on designing circuits using design constrains of Design vision, Primetime: Designed a combinational circuit, wrote design
constraints for it (using Design Vision/Primetime), simulated the circuit using VCS to check the expected outputs and generated reports for
the circuit with all the timing specifications. 100 % required output was obtained.
CMOS and VLSI:
Design and layout of a test logic circuit for a large VLSI system-on-a-chip (SOC): Designed a test logic circuit to perform read/write
operation of a two bit data through a bidirectional data pin. Created transistor level, gate level, floor plan of the circuit using Microsoft Visio
and the layout using L-Edit. 80% required output was obtained.
Analog and Mixed Signal IC Design:
Design of a 2-stage Op-amp: Modeled a two stage Op-amp and ran simulations using PSPICE to determine the UGBW, Phase margin, DC
open loop gain for the given specifications of the Op-amp. 100% specification satisfied design was obtained.
Micro-computer system Design I:
Design of a data transfer in PCI devices: Designed a data transfer in PCI devices between the initiator and the target using Verilog coding
and simulated using ModelSim to check the performance of the design. 100 % output was obtained.
IT Consulting Assistant ECS Computer lab, CSU Sacramento Fall 2007 to Fall 2008
Promoted as IT Helpdesk Coordinator ECS Computer lab, CSU Sacramento Spring 2009 to Present
Maintenance of Engineering and Computer Science labs
Coordinating meetings for lab assistants, recording meeting minutes and maintaining lab assistants’ schedules.
Assisting students/faculty/staff in solving their issues with computer system, different user application Softwares and printers.
Fixing printer/projector problems
Student Office Assistant ECS Deans Office, CSU Sacramento Fall 2007 to Fall 2009 (Sept’)
Received people; Attended phone calls; Recorded messages; Performed clerical work.
Microsoft Representative for Windows 7 Campus Entertainment Network Fall 2009 to present
Need to execute 200 trials of Windows 7 over a 10 week program.
Achieved the targeted 200 presentations of Win 7 in 5 weeks by presenting in classes, social networking, club meetings, on-campus
table demonstrations and in-lab trials.
Continuing the program successfully and exceeding the target.