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					Lecture 3:
VHDL Introduction
Part 3: Concurrent Processes
Outline


 The Process construct

 Process Statement Activation

 The Wait Statement
Quick Review


Questions

1. What the architecture of a VHDL model is composed of in order to
    support concurrency?
2. If the CSA statements are concurrent, how are they activated?

Answer

1. To support concurrency, the architecture of a model in VHDL is composed of
concurrent statements where each statement represents a separate unit of
functionality (CSA, Process, Component instantiation, etc.).

2. CSA statements are activated when an event occurs on a signal to which the
statement is sensitive. A CSA statement is then sensitive to any signals used/read in
making its assignment.
Note: Different rules apply for other concurrent statements (such as PROCESS, …).
Quick Review
Question: What is A delta () delay?
          A delta () delay is not an actual unit of time, but rather is just a concept where the time
          passed is considered so small that the simulation time does not advance.

1. For the following code, assume an event occurs on signal b randomly at,
   for example, 35ns. Complete the Table 1.
                                                                  Time       a      b      c   out_1
    BEGIN
      c <= (a AND b) AFTER 10ns;
      out_1 <= (c XOR b) AFTER 15ns;                               0ns       1      0      0     0
    END ARCHITECTURE example;                                     35ns       1      1      0     0




                                                                                 Table 1
2. For the following code, assume an event occurs                 Time       a      b      c   out_1
   on signal b randomly at, for example, 7ns.
                                                                   0ns       1      0      0     0
   Complete the Table 2.
   ARCHITECTURE example OF concurrency IS                          7ns       1      1      0     0
     SIGNAL c:std_ulogic;
   BEGIN
     c <= a AND b;
     out_1 <= c XOR b;
   END ARCHITECTURE example;                                                     Table 2
The Process Construct


 So far our modeling of digital circuits has been
  accomplished using CSA (concurrent signal assignment) statements.

     Each component in the hardware is characterized by the generation
      of events on output signals in response to input signals.

     The component behaviour is expressed with CSA statements that
      explicitly relate input signals, output signals, and delays.
The Process Construct


 What happens if we now want to construct much more
  complicated behaviours, such as memory access.

      We need to maintain state
      There will be many, many components
      More complicated data structures required
      It will be more difficult to abstract
The Process Construct


 How can we describe our models in more detail?

    The Process statement!

    This is another concurrent statement, like a simple CSA statement,
     except that it is composed of a number of sequentially executed
     statements.

    With these sequential statements we will see traditional
     programming constructs such as IF statements, loops, etc...
The Process Statement

 Format         [label:]PROCESS[(sensitivity list)] [is]
                   -- Declarative statements
                 BEGIN
                   --sequential activity statements
                 END PROCESS [label];
 Notes
     The label is optional, but is useful in documenting the model; as a good
      coding practice it will be considered required in our class.
     The is is optional; its use is required in our class.
 Example
 LIBRARY IEEE;
 USE IEEE.std_logic_1164.ALL;
 ENTITY and_gate IS
   PORT (a, b: IN std_ulogic;
         result: OUT std_ulogic);
 END ENTITY and_gate;
 ARCHITECTURE behaviour OF and_gate IS
 BEGIN
  calc: PROCESS(a,b) IS
  BEGIN
    result<=(a AND b) AFTER 5ns;
  END PROCESS calc;
 END ARCHITECTURE behaviour;
Process Statement Activation

 The Process statement can be thought of like an expanded view of a
  concurrent statement.
    The entire process is activated and executed in “zero” simulator time
    The process is concurrent with other concurrent statements.
        CSA statements are activated based on the signals to which they are sensitive as
         previously discussed.
        Similarly, the process statement is sensitive to particular signals...but which ones?


 There are 2 ways that a process statement is activated:
    The process may explicitly declare its sensitivity list; events on those signals
     activate the process.
    The process may include a WAIT statement within its sequential operations.
     Execution of the process remains at that segment of code until the conditions
     of the WAIT are met.

        Only ONE of these two choice may be used!
        Processes that declare a sensitivity list may not use wait statements and vice versa!
Process Statement Activation


 Our previous example demonstrated the use of a sensitivity list:
               ARCHITECTURE behaviour OF and_gate IS
               BEGIN
                 calc: PROCESS(a,b) IS
                 BEGIN
                   result<=(a AND b) AFTER 5ns;
                 END PROCESS calc;
               END ARCHITECTURE behaviour;

 How is a wait statement used?
The Wait Statement
 The WAIT statement is used within a process to control when the
  process is executed
    Without control, a process would execute continually
    Format:
                WAIT [ON list] [UNTIL condition] [FOR time];


    Allows a process activation based on a signal(s) event, until a condition is met,
     or for a specified period of time.

             WAIT ON a,b;      WAIT UNTIL CLK = ‘1’;        WAIT FOR 150 ns;


    Note that WAIT ON list is the same as using a sensitivity list. For example:
The Wait Statement



 Other examples of using wait statements:

    WAIT;
    WAIT ON a;
    WAIT FOR 50ns;
    WAIT ON b FOR 100ns;
    WAIT UNTIL a='1' FOR 50ns;
    WAIT ON a UNTIL(c='1')FOR 50ns;


 As can be seen, the wait statement allows for much more flexible
  behaviour to be modeled that CSAs

 More than one wait statement may be used in a process if
  required
The Wait Statement

 What do these do?




 The 1st process above executes once at the beginning of the VHDL simulation
  and then suspends until the input A is assigned a value of ‘1’ before it executes
  again. This cycle continues in that the process executes every time A is assigned
  a value of ‘1’.

 The 2nd process also executes once at the beginning of the VHDL simulation, but
  it then waits for 100ns of simulation time and executes again. This cycle
  continues with the process executing every 100ns of simulation time.
Wait Statement Interaction

 Examples:


      WAIT ON a UNTIL(a='0'); --The ON a is redundant
      WAIT ON a UNTIL(b='1'); --Passes when b is
                              --already '1' and an
                              --event occurs on a.
                              --Changes solely on b do
                              --not pass the statement
      WAIT ON a UNTIL(b='1') FOR 50ns; --Passes as
                                       --described
                                       --above, but
                                       --will wait no
                                       --longer than
                                       --50ns.
The Wait Statement
 Example of more complex behavior: a positive-edge-triggered D flip-flop
    Activation should occur only on a 01 transition
        To help with this, an attribute can be used from a signal to detect if it has changed (ie: from
         0 1 or from 1 0). The syntax for this is signal_name'EVENT
    Note that our example will not include the set/reset behavior normally expected from
     a flip-flop


 Note the placement of the Wait                   LIBRARY IEEE;
                                                   USE IEEE.std_logic_1164.ALL;
  statement in the example
                                                ENTITY d_ff IS
                                                  PORT (d, clk: IN std_ulogic;
                                                        q, qbar: OUT std_logic);
    Even with a sensitivity list, a process is END ENTITY d_ff;
     always executed at least once.                ARCHITECTURE behaviour OF d_ff IS
    If this is not the desired behavior,          BEGIN
     a wait on statement placed at the               output: PROCESS
                                                     BEGIN
      beginning of a process ensures that              WAIT UNTIL(clk'EVENT AND clk='1');
      no execution occurs until activity on            q<=d AFTER 5ns;
                                                       qbar<=NOT d AFTER 5ns;
      the desired signal.                            END PROCESS output;
                                                   END ARCHITECTURE behaviour;
To model simply a FF
 -- simplest DFF template (not recommended)
 Q <= D when rising_edge(CLK);
   -- recommended DFF template:
   process(CLK)
   begin -- use falling_edge(CLK) to sample at the falling edge instead
       if rising_edge(CLK) then Q <= D; end if;
   end process;
   -- alternative DFF template:
   process
   begin
       wait until CLK='1'; Q <= D;
   end process;
   -- alternative template expands the ''rising_edge'' function above:
   process(CLK)
   begin
      if CLK = '1' and CLK'event then --use rising edge, use "if CLK = '0' and CLK'event" instead for falling edge
      Q <= D;
   end if;
   end process;
Review


Questions

1. How are Process statements activated?
2. What are the 3 forms of a Wait statement? (explain each)
3. Which form of the Wait statement is like using a sensitivity list?

Answer

1. Waiting list or with WAIT statement. Exp. PROCESS(a, b, c).
2. These are the 3 forms of a WAIT statement.



3. WAIT ON is like using a sensitivity list.
The Declarative Region


  Recall the format for a Process statement:
  [label:]PROCESS[(sensitivity list)] [is]
    -- Declarative statements
  BEGIN
    --sequential activity statements
  END PROCESS [label];



  What can be declared in the declarative region?

     We have not been explicit about this issue until now!
The Declarative Region


  Where may each object be declared?
     Signals:
        As ports in an entity declaration
        In the declarative region of an entity
        In the declarative region of an architecture
     Variables:
        In the declarative region of a process
        In the declarative region of a subprogram (to be seen)
     Constants:
        In   an the declarative region of an entity
        In   the declarative region of an architecture
        In   the declarative region of a process
        In   the declarative region of a subprogram (to be seen)
Variable Usage in Processes

 While signals may be assigned by a process, only variables (and
  constants) may be declared

    Variables exist within the scope of the process and are persistent; they exist for the life
     of the simulation
    They are of the same type as signals, variables may then be assigned the value of a
     signal and vice versa
    The := operator is used to assign a value to a variable.

                 new_nand: PROCESS(a,b) IS
 Example:         VARIABLE intermediate:std_ulogic;
                 BEGIN
                   intermediate:= a AND b;
                   c<=NOT intermediate;
                 END PROCESS new_nand;

    Note in the declaration the variable also could have had an initialization, ie:

                          VARIABLE intermediate:std_ulogic:='0';

    Note the example assumes signals a,b,c declared of type std_ulogic
Process: Signals vs. Variables

 Previously, we learned that processes are concurrent statements and
  are executed at the same time as other concurrent statements

    However, the code within a process is executed sequentially
    What does this mean for variable and signal assignments?
    SIGNAL num, sum:integer;
    --Above declaration is in architecture
    -- declarative region.
    ex_signal: PROCESS IS
    BEGIN
      WAIT FOR 10ns;
      num <= num+1;
      sum <= sum+num;
    END PROCESS ex_signal;

    ex_variable: PROCESS IS
      VARIABLE num, sum:integer:=0;
    BEGIN
      WAIT FOR 10ns;
      num := num+1;
      sum := sum+num;
    END PROCESS ex_variable;
Process: Signals vs. Variables

             PROCESS ex_signal                 PROCESS ex_variable

     Time         num            sum    Time         num             sum

       0            0             0      0            0               0

      10            0             0      10           1               1

     10+           1             0     10+          1               1

      20            1             0      20           2               3

     20+           2             1     20+          2               3

      30            2             1      30           3               6

     30+           3             3     30+          3               6

  SIGNAL num, sum:integer;
  --Above declaration is in
  architecture                         ex_variable: PROCESS IS
  -- declarative region.                 VARIABLE num, sum:integer:=0;
                                       BEGIN
  ex_signal: PROCESS IS                  WAIT FOR 10ns;
  BEGIN                                  num := num+1;
    WAIT FOR 10ns;                       sum := sum+num;
    num <= num+1;                      END PROCESS ex_variable;
    sum <= sum+num;
  END PROCESS ex_signal;
Process: Signals vs. Variables

  This behaviour is caused because variable assignments
   happen immediately

     If variable x is assigned the value 5 and is read on the next line of
      code, it will return 5

     If signal x has the value 0, is then assigned the value 5 and is read
      on the next sequential line of code, it will return 0

         This will be true for other concurrent statements that read signal x until
          the next delta!


     We will now see why signals are different than variables...
Terminology

  Assignments made to signals are comprised of time-
   value pairs, eg: ‘1’-5ns, ‘0’-10ns, ‘1’-15ns, ‘0’-20ns

  a<=NOT b AFTER 5ns;

  These assignments represent future values of the
   signal and are referred to as transactions

  Since assignments can be made for any point in the
   future, the simulator must keep an ordered list of
   these transactions for a signal

     This list is held by the driver of the signal
Drivers

 A driver for a signal contains a projected output waveform for that
  signal
     An assignment to a signal creates a driver for that signal
     This means that each concurrent statement has an associated driver with a projected
      output waveform
         For example ‘1’-5ns, ‘0’-10ns, ‘0’-18ns, ‘1’-19ns OR

     Each signal assignment affects the projected output waveform by adding and possibly
      deleting transactions on that waveform

 So far, we have seen only situations that would add a single transaction
  to a driver
     How could multiple transactions be placed on a projected output waveform?
         A CSA statement could assign many values at once:
         Sig <= 0 after 100ns,
                8 after 20ns,
                2 after 40ns,
                5 after 65ns,
                10 after 100ns;
Drivers
 How could multiple transactions be placed on a projected output
  waveform?

    A process could assign to the same signal in multiple lines of its sequential code:

                   ex_signal: PROCESS IS
                   BEGIN
                     WAIT FOR 10ns;
                     num<=num+1 after 2ns;
                     num<=transport num+2 after 10ns;
                     sum<=sum+num;
                   END PROCESS ex_signal;
Drivers

  Could multiple concurrent statements assign to the same signal?

     Yes and no.

     When multiple concurrent statements
      are driving the same signal there
      exists a conflict between the drivers.

     If your model must have multiple
      drivers for the same signal then you
      must provide a resolution function
      to determine the outcome.


          More will be seen on resolution
           functions (which are a type of
           subprogram) later in the course...
More about signal assignments in the process


...
BEGIN
         PROCESS
         BEGIN
         ...
         x <= a; -- this assignment is executed before the next one.
         y <= b;
         ...
         END PROCESS;
...




... – Scheduling example
BEGIN
          PROCESS
          BEGIN
          ...
          x <= a AFTER 10 NS; -- the value of a is scheduled for x after 10ns
          y <= b AFTER 6 NS; -- the value of b is scheduled for y after 6 ns
          ...
          END PROCESS;
...
-- first assignment b to y is executed
-- then in 4 ns, assignment a to x is executed
-- signal y receives the value of b 4 ns sooner than x, even though the
-- scheduling of the former was done after that of the latter.
More about signal assignments in the process




...
BEGIN
         PROCESS
         BEGIN
         ...
         x <= `1`; -- `1` is scheduled for x after delta delay;
         IF x=`1` THEN -- this statement is executed immediately after the execution of x<=`1` assignment;
                   action_1;
         ELSE
                   action_2;
         END IF
         ...
         END PROCESS;
...

-- Since these two statements (x<=... and IF) are executed during the same simulation cycle
-- (in zero time), the new `1` value of x is not available for the IF.
-- Had x been a variable (x:=`1`), its new value, `1`, would be available
-- (action_1 would have been performed).
Questions

				
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