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EECS 413 Project 1 A Low Voltage Bandgap Reference Circuit with Current Feedback Tao Li, Bhaskar Mitra, and Kabir Udeshi Abstract—This paper describes the design of a bandgap II. CIRCUIT DESCRIPTION reference, implemented in 0.25µm CMOS technology. The circuit A reference voltage is generated by adding two voltages generates a reference voltage of 1.157V and has a temperature coefficient of 0.03mV/K at 27C. It can operate with supply that have temperature coefficients of opposite sign with voltages between 2.25V and 2.75V and between 0C and 85C. It suitable multiplication constants. The resulting voltage has a PSRR of 59dB under normal operating conditions. This obtained is independent of temperature. The diode voltage circuit works in a current feedback mode, and it generates its drop across the base-emitter junction, VBE, of a Bipolar own reference current, resulting in a stable operation. A startup Junction Transistor (BJT) changes Complementary to circuit is required for successful operation of the system. Absolute Temperature (CTAT) [1]. Whereas if two BJTs operate with unequal current densities, then the difference in I. INTRODUCTION the base emitter voltages, ∆VBE, of the transistors is found to O NE of the essential building blocks of many analog circuits is a voltage reference, which should exhibit little dependence on supply and process parameters and a well be Proportional to Absolute Temperature (PTAT). The PTAT relationship is given by [2], ∆ V BE = VT ln m ; VT = kT / q (1) defined dependence on temperature. For example, accurate biasing voltages are critical for many circuit schemes; in where, k is Boltzmann’s constant, T is the absolute ADC, a reference voltage is required to quantify an input, temperature, q is the electron charge and m is the ratio of the while in DAC, it is required to define the output full-scale current densities of the two BJTs. The PTAT voltage may be range. added to the CTAT voltage with suitable weighting constants As a well-established reference generator technique, to obtain a constant reference voltage. bandgap reference is most popular for both Bipolar and Figure 1 shows the block diagram of the badgap reference CMOS technologies. The principle of the bandgap circuits circuit designed. By using a supply independent current relies on two groups of diode-connected BJT transistors source, a current ISS is passed through BJT A. The same running at different emitter current densities. By canceling the current ISS flows through m transistors connected in parallel, negative temperature dependence of the PN junctions in one identical to A. Thus the current density of A is m times the group of transistors with the positive temperature dependence current density of the m BJTs identical to A, connected in from a PTAT (proportional-to-absolute-temperature) circuit parallel. The voltages at node X and Y are maintained at the which includes the other group of transistors, a fixed DC same value, VBE using a feedback network through a voltage which doesn’t change with temperature is generated. differential amplifier. This results in a voltage of ∆VBE, This voltage is typically 1.26 volts, which is approximately across the resistor R. The voltages VBE and ∆VBE are added to the band gap of silicon. [3][4] Startup Supply Independant There are many different implementation reported, while Circuit Current Source essentially a bandgap reference circuit consists of a supply- independent biasing circuit, a diode connected BJT transistor generating a voltage with negative temperature coefficient, a Iss Iss PTAT circuit and some kind of feedback mechanism to X Y improve the performance. In this work, a measurement and addition circuit is implemented to output the reference R1 Delta VBE voltage. Current mirrors with current feedback mechanism are used to minimize supply dependence. Feedback mechanism is VBE implemented by simple 2-stage single-ended differential Measure & mA A amplifier. The circuit has been optimized for minimum Add Voltages temperature and supply dependence with simplest implementation. Fig. 1: Block diagram of Bandgap Reference Circuit. EECS 413 Project 2 C E B arrangement to generate the reference voltage while conserving voltage headroom. The circuit has a stable operating point at which no current p+ p+ n+ to flows through it. An arrangement must be made to force the saturation when the supply is turned on. This function is n-well carried out by the startup circuit. p-substrate III. CIRCUIT ANALYSIS Fig. 2: pnp BJT using CMOS process.. obtain the reference voltage. The circuit also requires a A. Bandgap Core startup circuit since there exists a stable state at which no The bandgap reference voltage is generated by adding the current flows through the circuit. The startup circuit forces base emitter voltage, VBE, of a BJT to the difference in base the transistors to turn on and the circuit to operate at its other emitter voltage, ∆VBE, of BJTs with a ratio of current density stable state to generate the reference voltage. m. In order to generate a stable circuit, it is necessary to keep It should be noted that an ideal BJT is not available in the BJT in the exponential region. By simulating the CMOS technology. A pnp BJT is made using the n-well transistor characteristics it was found that the minimum value normally associated with a PFET [1] (Figure 2), the p- of collector current that could be used is 10 µA (Figure 4). By substrate behaving as the collector. selecting a current density ratio of 8, and a minimum collector current of 12.5 µA, we obtain a ∆ VBE of 52 mV using In order to generate supply independent current and carry Equation 1. The total collector current is 100 µA, which out an addition of the CTAT and PTAT voltages, the circuit in allows the resistor R1 to be in the order of hundreds of ohms. Figure 3 is used. The OPAMP provides the base voltage to It would be difficult to implement a smaller value of resistance the transistors which are connected as current mirrors. By using the 0.25 µm IBM process. selecting the value of R1 and current ISS, the circuit may be The value of the resistor R1 is calculated buy dividing the designed to operate at the desired operating point. The value voltage by the current and turns out to be a value of 465 Ω of R1 is given by, (Equation 2). By setting R2 we determine the multiplication R1 = ∆ V BE / I SS (2) constant of the circuit. R2 is calculated using Equation 3 and Since the same current ISS flows through R2, the voltage at turns out to be 4.65 KΩ. the output reference voltage nodes is given by, The transistors in the circuit are sized to operate with a R1 (3) VDSAT of 0.4 V. We use the current equation [1] to determine Vref = V BE + ∆ V BE . R2 the size of the current source transistors, TP1 and TP2. Thus by selecting the value of R2 the weighting constant 1 W (4) I D = µ C OX 2 V DSAT may be set. This arrangement provided an elegant 2 L Startup Add CTAT and Bandgap Core with supply OPAMP Circuit PTAT Voltages independant current source VDD TN2 TP4 TP3 TP2 TP1 TP5 TP6 Iss Iss Iss TP7 TP8 TN3 TN7 ∆ VBE.R2/R1 TN1 + VBE R2 ∆ VBE R1 VBE TN4 TN5 TN6 A mA A Fig. 3: Schematic of Bandgap Reference Circuit showing the supply independent current source and generation of reference voltage.. EECS 413 Project 3 TABLE I DEVICE SIZES Component Value (µm) TP1,TP2, TP3, TP5, TP6 52/2 TP7, TP8 26/2 TP4 2/5 TN1, TN3 20/1 TN2 2/5 TN4, TN5 6.6/2 TN6, TN7 13/2 R1 464 Ω R2 4.13 KΩ mirror circuit with a PMOS driver was selected. The output common mode voltage corresponds to the gate voltage of the current mirror transistors. In order to have a VDSAT of 0.4 V for these transistors the output common mode Fig. 4: The relation between the base-emitter voltage and the collector current should be ideally about 1.5 V. A second stage was added to of the BJT ceases to be logarithmic below about 10 µA of collector current. the OPAMP to increase gain and shift the common mode voltage up by using an NMOS driver. The NMOS driver only Where, ID is the drain current, µ is the mobility of the provided an output common mode of about 0.4 V. By adding carriers, COX is the oxide capacitance per unit area, W is the a diode-connected transistor, TN7, to the second stage, the width, and L the length of the transistors. output voltage was pushed up to about 1.3 V without any The value of the W/L is 26. A length of 2 µm was used to effect on the gain of the stage. The voltage drop accress the reduce the effect of channel length modulation. The diode connected transistor is about 1.2 V corresponding to dependence on the OPMAP gain may be reduced if channel VTH + VDSAT. The gain of each of the stages of the OPAMP is length modulation is minimized. A longer channel also given by improves circuit symmetry making it less sensitive to process Av = gm .R O (7) variation and giving it the ability to generate stable currents. In order to have the VBE of a BJT vary linearly with where, Av is the gain, gm is the transconductance of the temperature, the collector current of the BJT must be constant. driving transistor and RO is the effective output resistance at However, in the circuit used the collector current changes with the output node. The gain of each stage is about 42; the temperature. The variation of VBE with temperature can be differential pair with a non-inverting gain and the single stage expressed using the relation [1], with an inverting gain ∂ V BE V BE − ( 3 + m )VT − Eg / q (5) = ∂T T Where, Eg is the bandgap voltage of the semiconductor material, q is the electron charge and T is the temperature in K. This relationship can be solved only numerically and is plotted in Figure 4. By using the analytical estimation we see that VBE does not change linearly with temperature. Using this relationship the estimation of change of the reference voltage with temperature is estimated to be 0.011 V over the temperature range from 300 to 385 K. Temperature (K) ⎡ ∂V ∂ V BE ⎤ (6) ∆ Vref = ∫ ⎢ BE − ⎥ dT ⎣ ∂T ∂ T T → 300 K ⎦ Fig. 5: Analytical estimation of nonlinearity of rate of change of VBE with temperature. B. OPAMP The OPAMP was used to maintain equal node voltages and C. STARTUP CIRCUIT provide a feedback to maintain the drain currents constant and Transistors TN1, TN2, TN3 and TP4 constitute the startup insensitive to supply variations. A high gain of the OPAMP circuit. Initially all the transistors start off in off state. The would result in better voltage tracking of nodes X and Y voltage at the gate of TN1 is low and so it remains in off (Figure 1). The common mode voltages play an important state. TP4 being diode connected is always on and so the role in determining the OPAMP topology. The input common transistor TN2 turns on forcing the drain to a low value. The mode was determined by the base emitter voltage of the BJT, current mirror stack turns on and the gate voltage of TN1 which is 0.8 V at 100 µA of collector current. In order to rises and it starts to conduct. At this point there is a meet the input common mode condition an active current competieion between the output of the amplifier TP6, and EECS 413 Project 4 TN2 for the current source load. TN2 is designed to be a weak transistor with W/L of 1/5 so the amplifier takes control of the current mirror gate. When the bandgap voltage is high enough ( ~1V) the transistor TN1 turns on. TN1 in linear region has to compete with TN2 in saturation so it is designed to be a big transistor. It draws all the current from TP2 and the base voltage of TN2 falls till it turns off. In this state the gate voltage at TN2 is about 0.6 V. This is high enough for the transistor TN1 to be conduct slightly. A diode connected transistor TN3 is added to increase the threshold voltage at the gate of TN3 to turn off. The transistor TP4 is designed to be a weak device so that low current flows through the parasitic path when the circuit is in full operation. Figure 7: Variation of the reference voltage with supply voltage at 27C IV. RESULTS The bandgap reference voltage gives a voltage of 1.1570V Figure 8 shows the a.c response. A PSRR of 59dB is obtained when adjusted to have a zero temperature coefficient at 27C. at d.c at the high frequency corner of 10Mhz, the PSRR starts Figure 1, shows the result of the simulation. It can be adjusted to degrade ans is about 10dB for a frequency of abou 20Mhz. to give a voltage of 1.26V, by sacrificing the zero temperature This problem can be solved by putting a 100pF capacitor coefficient at 27C, but this leads to a much more degraded between Vdd and ground to suppress the noise in Vdd. This response. Figure 5, shows the result of the simulation. As can would probably be done external to the chip as it is not be seen an overall temperature coefficient of 0.1mV/K is feasible to put the supply bypass capacitor on-chip. obtained between 0C and 85C, which corresponds to about 0.5% variation. The response it worse for temperatures from 65-85C with a temperature coefficient of 0.2mV/K. Below these temperatures the temperature coefficient is 0.03mV/K. Figure 8: PSRR of the circuit at 27C The D.C characteristics at 85degrees are shown in figure 9. The variation with Vdd is much worse in this case. The nominal value at 2.5V is still 1.1570V but at low Vdd it degrades to 1.100V, a 6%variation in voltage. Figure 6: Variation of bandgap reference with temperature at Vdd=2.5V Figure 10, shows the PSRR of the circuit at 85C. It comes down from 60dB at 27C to about 30dB in this case. This Figure 7 shows the variation when the supply voltage is varied degradation in characteristics is probably due to degradation from 2.5V to 2.75V. The relative variation is 0.32%. at 27C. in the gain of the amplifier, which increases the error voltage Even here the response shows a two fold characteristic. The that needs to be sustained to drive the circuit. response is much better in the high voltage range 2.2-2.75 than in the low voltage range (2.25V-2.4V). So the worst case operation of the device is at 85C and a supply voltage of 2.25V. EECS 413 Project 5 VI. CONCLUSION A bandgap reference with a current feedback mode has been designed. The circuit uses no external current sources and is designed to have a zero temperature coefficient at 27C. The design is implemented with 0.25µm CMOS process and consumes very little headroom. The output voltage is 1.1570V at the nominal operating condition of 27C temperature and 2.5V supply voltage. It has a temperature coefficient of 0.03mV/K from 0-60C. It has a PSRR of 59dB and a large signal variation of 0.32% with Vdd under nominal operating conditions. The circuit performance degrades at higher Figure 9: Variation with Supply Voltage at 85C (absolute worst case) temperatures and lower voltages. In the worst case corner of high temperature (85C) and low supply voltage (2.25V) the circuit puts out 1.100 volt, a 5% variation from the nominal value. TABLE 2: REFERENCE VOLTAGE OBTAINED UNDER DIFFERENT SUPPLY VOLTAGES AND TEMPERATURES 2.5V 2.25V 2.75V 27C 1.157V 1.1555V 1.1573V 85C 1.156V 1.100V 1.157V REFERENCES Figure 10: PSRR at 85C [1] B. Razavi, Design of Analog CMOS Integrated Circuits. New york, NY: 2001, ch 11. [2] D. Hilbiber, “A New Semicondictor Voltage Standard,” IEEE J. of Solid-State Circuits, vol. 8, pp. 222-226, June 1973. V. LAYOUT [3] Robert A. Pease, “The Design of Band-Gap Reference Circuits: Trials and Tribulations,” IEEE Proc. of the 1990 Bipolar Circuits and Figure 9 shows the layout. The chip occupies a total area of . Technology Meeting, Minneapolis, Minnesota , Sept. 1990 The chip has been optimized by combining all the FETs. Most [4] K. Lasanen, V. Koorkala, etc., “Design of A 1-V Low Power CMOS of the area is taken up by the pnp transistors, so it cannot be Bandgap Reference Based on Resistive Subdivision,” IEEE 2002 optimized too much [5] T. Brooks and A.C Westwisk, “ A low power differential CMOS bandgap Reference”, ISSCC Dig. Of Tech. Papers, pp 248-249, Feb 1994 [6] K. Lasanen, et. Al, “ Design of a 1-V low power bandgap reference based on Resistive Subdivision”, Proceedings of the 45th IEEE Midwest Symposium on Circuits and Systems, Tulsa, Oklahoma, USA, August 2002 Figure 7: Layout of the bandgap reference circuit . APPENDIX The simulation files are in /afs/engine.umich.edu/class/f03/eecs413/group3/bandgap/bandgap/concept_low_volt_test_sim