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					                                                  Table ORTC-1 ITRS Technology Trend Targets




Table ORTC-1 ITRS Technology Trend Targets

Year of Production                                            2009       2010      2011        2012      2013     2014     2015     2016
Flash ½ Pitch (nm) (un-contacted Poly)(f)[2]                   38         32        28         25            23    20       18       15.9
DRAM ½ Pitch (nm) (contacted)[1,2]                             52         45        40         36            32    28       25       22.5
MPU/ASIC Metal 1 (M1) ½ Pitch (nm)[1,2]                        54         45        38         32            27    24       21       18.9
MPU Printed Gate Length (GLpr) (nm) ††[1]                      47         41        35         31            28    25       22       19.8
MPU Physical Gate Length (GLph) (nm)[1]                        29         27        24         22            20    18       17       15.3

ASIC/Low Operating Power Printed Gate Length (nm) ††[1]        54         47        41         35            31    25       22       19.8
ASIC/Low Operating Power Physical Gate Length (nm)[1]          32         29        27         24            22    18       17       15.3
ASIC/Low Standby Power Physical Gate Length (nm)[1]            38         32        29         27            22    18       17       15.3
MPU Etch Ratio GLpr/GLph (nm)[1]                              1.6039    1.5296     1.4588    1.4237     1.3895    1.3561   1.3235   1.2917




                                     The International Technology Roadmap for Semiconductors, 2009 Edition
                                                          Table ORTC-1 ITRS Technology Trend Targets




Table ORTC-1 ITRS Technology Trend Targets

Year of Production                                                 2017      2018       2019      2020       2021      2022     2023     2024
Flash ½ Pitch (nm) (un-contacted Poly)(f)[2]                       14.2      12.6       11.3       10.0       8.9       8.0      7.1      6.3
DRAM ½ Pitch (nm) (contacted)[1,2]                                 20.0      17.9       15.9       14.2      12.6       11.3     10.0     8.9
MPU/ASIC Metal 1 (M1) ½ Pitch (nm)[1,2]                            16.9      15.0       13.4       11.9      10.6       9.5      8.4      7.5
MPU Printed Gate Length (GLpr) (nm) ††[1]                          17.7      15.7       14.0       12.5      11.1       9.9      8.8      7.9
MPU Physical Gate Length (GLph) (nm)[1]                            14.0      12.8       11.7       10.7       9.7       8.9      8.1      7.4

ASIC/Low Operating Power Printed Gate Length (nm) ††[1]            17.7      15.7       14.0       12.5      11.1       9.9      8.8      7.9
ASIC/Low Operating Power Physical Gate Length (nm)[1]              14.0      12.8       11.7       10.7       9.7       8.9      8.1      7.4
ASIC/Low Standby Power Physical Gate Length (nm)[1]                14.0      12.8       11.7       10.7       9.7       8.9      8.1      7.4
MPU Etch Ratio GLpr/GLph (nm)[1]                                  1.2607    1.2304     1.2008     1.1720    1.1438     1.1163   1.0895   1.0633




                                               The International Technology Roadmap for Semiconductors, 2009 Edition
                                                       Table ORTC-1 ITRS Technology Trend Targets




Table ORTC-1 ITRS Technology Trend Targets

Year of Production                                                         2009           2010            2011           2012           2013            2014           2015         2016
Notes for Table ORTC-1
†† MPU and ASIC gate-length (in resist) node targets refer to the most aggressive requirements, as printed in photoresist (which was by definition also “as etched in
polysilicon,” in the 1999 ITRS).

However, during the 2000/2001 ITRS development, trends were identified, in which the MPU and ASIC “physical” gate lengths may be reduced from the “as-printed”
dimension. These physical gate-length targets are driven by the need for maximum speed performance in logic microprocessor (MPU) products, and are included in the Front
End Processes (FEP), Process Integration, Devices, and Structures (PIDS), and Design chapter tables as needs that drive device design and process technology requirements.

Refer to the Glossary for definitions of Introduction, Production, InTERgeneration, and InTRAgeneration terms.

MPU Physical Gate Length targets were significantly revised in the 2008 Update from previous ITRS roadmap document to align with survey and data updates from the PIDS
and FEP TWGs. The MPU physical gate length targets are now set based on a modeled trend for a 3.8-year cycle (0.5x per7.6 years), which is a best-fit to the survey update
data. Additional revision of the gate length line item targets occurred in the 2009 roadmap work. The line items were shifted one year to align with actual data, which indicated
that leading-edge gate lengths were able to remain constant for an additional year, due to trade-offs with gate process enhancements (known as "equivalent scaling"). The
MPU printed gate length has been adjusted to reflect the agreement between the FEP and Lithography TWGs to use a variable ratio factor, to model the relationship between
the final physical gate length and the printed gate length, after additional processing is applied to printed gate length isolated feature. The new variable ratio targets can be
seen above in the "MPU Etch Ratio" line item. The ASIC/Low Operating Power gate length targets are likewise adapted to the new PIDS survey data (by shifting their
introduction timing relative to the MPU printed and physical gate lengths); and a new Standby Physical Gate Length was added in the 2008 Update.

MPU/ASIC M1 stagger-contact interconnect targets have been significantly adusted in the 2009 roadmap. The industry data has indicated that the estimated 2.5-year
technology cycle is actually a 2-year cycle, which initially is delayed from the unchanged DRAM M1 2.5-year cycle trend. As can be noted in the data above, the MPU M1 2-
year technology cycle trend is now expected to cross over the DRAM M1 trend in 2010/45nm and continue until 2013/27nm, when it is expected to turn to a 3-year cycle rate.
Confirmed by the latest PIDS surveys, the unchanged DRAM M1 targets are still expected to turn from a 2.5-year cycle to a 3-year cycle in 2010 and remain on the 3-year cycle
trend through 2024/8.9nm. After MPU M1 crosses DRAM, MPU lithography technology will begin to drive leading-edge lithography, along with Flash technology, which has
been extended on a 2-year cycle rate through 2010/32nm for the Flash uncontacted poly interconnect half-pitch [note: technology cycle timing definition: n-year cycle = 0.5x
reduction rate per 2n years].



Numbers in the header are rounded from the actual trend numbers used for calculation of models in ITRS ORTC and ITWG tables (see discussion in the Executive Summary
on rounding practices).
Beyond 2016, the numbers are rounded to one decimal point.




                                      The International Technology Roadmap for Semiconductors, 2009 Edition
                                                               Table ORTC-1 ITRS Technology Trend Targets




Table ORTC-1 ITRS Technology Trend Targets

Year of Production                                                         2017           2018            2019           2020           2021            2022           2023         2024
Notes for Table ORTC-1
†† MPU and ASIC gate-length (in resist) node targets refer to the most aggressive requirements, as printed in photoresist (which was by definition also “as etched in
polysilicon,” in the 1999 ITRS).

However, during the 2000/2001 ITRS development, trends were identified, in which the MPU and ASIC “physical” gate lengths may be reduced from the “as-printed”
dimension. These physical gate-length targets are driven by the need for maximum speed performance in logic microprocessor (MPU) products, and are included in the Front
End Processes (FEP), Process Integration, Devices, and Structures (PIDS), and Design chapter tables as needs that drive device design and process technology requirements.

Refer to the Glossary for definitions of Introduction, Production, InTERgeneration, and InTRAgeneration terms.

MPU Physical Gate Length targets were significantly revised in the 2008 Update from previous ITRS roadmap document to align with survey and data updates from the PIDS
and FEP TWGs. The MPU physical gate length targets are now set based on a modeled trend for a 3.8-year cycle (0.5x per7.6 years), which is a best-fit to the survey update
data. Additional revision of the gate length line item targets occurred in the 2009 roadmap work. The line items were shifted one year to align with actual data, which indicated
that leading-edge gate lengths were able to remain constant for an additional year, due to trade-offs with gate process enhancements (known as "equivalent scaling"). The
MPU printed gate length has been adjusted to reflect the agreement between the FEP and Lithography TWGs to use a variable ratio factor, to model the relationship between
the final physical gate length and the printed gate length, after additional processing is applied to printed gate length isolated feature. The new variable ratio targets can be
seen above in the "MPU Etch Ratio" line item. The ASIC/Low Operating Power gate length targets are likewise adapted to the new PIDS survey data (by shifting their
introduction timing relative to the MPU printed and physical gate lengths); and a new Standby Physical Gate Length was added in the 2008 Update.

MPU/ASIC M1 stagger-contact interconnect targets have been significantly adusted in the 2009 roadmap. The industry data has indicated that the estimated 2.5-year
technology cycle is actually a 2-year cycle, which initially is delayed from the unchanged DRAM M1 2.5-year cycle trend. As can be noted in the data above, the MPU M1 2-
year technology cycle trend is now expected to cross over the DRAM M1 trend in 2010/45nm and continue until 2013/27nm, when it is expected to turn to a 3-year cycle rate.
Confirmed by the latest PIDS surveys, the unchanged DRAM M1 targets are still expected to turn from a 2.5-year cycle to a 3-year cycle in 2010 and remain on the 3-year cycle
trend through 2024/8.9nm. After MPU M1 crosses DRAM, MPU lithography technology will begin to drive leading-edge lithography, along with Flash technology, which has
been extended on a 2-year cycle rate through 2010/32nm for the Flash uncontacted poly interconnect half-pitch [note: technology cycle timing definition: n-year cycle = 0.5x
reduction rate per 2n years].



Numbers in the header are rounded from the actual trend numbers used for calculation of models in ITRS ORTC and ITWG tables (see discussion in the Executive Summary
on rounding practices).
Beyond 2016, the numbers are rounded to one decimal point.




                                              The International Technology Roadmap for Semiconductors, 2009 Edition
2009 LINKS AND TABLE LIST

TABLE LINKS


ORTC Tables

FOCUS A Tables

FOCUS B Tables

FOCUS C Tables

FOCUS D Tables

FOCUS E Tables

FOCUS F Tables

CROSS CUT A Tables

CROSS CUT B Tables

2009 ITRS Table Listing

2009 ITRS Chapter Page
ND TABLE LIST




           Overall Technology Roadmap Characters. (Key Roadmap Drivers)

           Test & Test Equipment         |    RF and AMS for Wireless

           Emerging Research Devices (ERD)              |   Emerging Research Materials (ERM)

           Front-end Processes (FEP)            |   Process Integration, Devices, & Structures (PIDS)

           Lithography      |       Factory Integration

           Interconnect         |   Assembly and Packaging

           System Drivers | Design

           Environment, Safety, & Health (ESH)      |     Metrology   |   Modeling & Simulation

           Yield Enhancement

           2009 ITRS tables and titles list

           2009 ITRS page of reports online
               Below is a key showing the old ORTC table numbers versus the new 2009 ORTC table numbers

2008 Table #       2009 Table #     2008 Title                                            2009 Title
                                    Product Generations and Chip Size Model Technology
Table 1a&b     Table ORTC-1                                                               ITRS Technology Trend Targets
                                    Trend Targets
                                    DRAM and Flash Production Product Generations and     DRAM and Flash Production Product Generations and
Table 1c&d     Table ORTC-2A
                                    Chip Size Model                                       Chip Size Model
                                    DRAM Introduction Product Generations and Chip Size   DRAM Introduction Product Generations and Chip Size
Table 1e&f     Table ORTC-2B
                                    Model                                                 Model
                                    MPU (High-volume Microprocessor) Cost-Performance     MPU (High-volume Microprocessor) Cost-Performance
Table 1g&h     Table ORTC-2C
                                    Product Generations and Chip Size Model               Product Generations and Chip Size Model
                                    High-Performance MPU and ASIC Product Generations     High-Performance MPU and ASIC Product Generations
Table 1i&j     Table ORTC-2D
                                    and Chip Size Model                                   and Chip Size Model
Table 2a&b     Table ORTC-3         Lithographic-Field and Wafer Size Trends              Lithographic-Field and Wafer Size Trends
                                    Performance of Packaged Chips: Number of Pads and
Table 3a&b     Table ORTC-4                                                               Performance and Packaged Chips Trends
                                    Pins
               combine into Table
Table 4a&b                          Performance and Package Chips: Pads, Cost
               ORTC-4
               combine into Table   Performance and Package Chips: Frequency On-chip
Table 4c&d
               ORTC-4               Wiring Levels
Table 5a&b     Table ORTC-5         Electrical Defects [**]                               Electrical Defects [**]
Table 6a&b     Table ORTC-6         Power Supply and Power Dissipation                    Power Supply and Power Dissipation
Table 7a&b     Table ORTC-7         Cost                                                  Cost

				
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