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60 actel esd (PowerPoint)

VIEWS: 3 PAGES: 22

  • pg 1
									Briefing: Independent NASA
  Test of RTSX-SU FPGAs

    RT54SX-S & RTSX-SU
    ESD Performance
 ESD
 What is ESD (Electro Static Discharge)?

   A Transfer of electrostatic charge between two
       bodies at different electrostatic potentials




ESD Characterization                        Date of Presentation   2
 ESD Test Models
 Different types of ESD Test Models
 CDM (Charge Device Model)
         A specified circuit characterizing an ESD event that occurs when a
          device acquires charge through some triboelectric or electrostatic
          induction processes and then abruptly touches a grounded object
          or surface (JEDEC STD No 22-C101C)
 MM (Machine Model)
         Machine Model simulates a more rapid and severe electrostatic
          discharge from a charged machine, fixture, or tool. (JESD22-A115)
 HBM (Human Body Model)
         Direct transfer of electrostatic charge through a significant series
          resistor from the human body or from a charged material to the
          electrostatic discharge sensitive (ESDS) device
                 JESD22-A114
                 TM3015.7 (MIL-STD-883F )




ESD Characterization                                                Date of Presentation   3
 ESD Pin Groupings
 JEDEC
         All IO’s (including JTAG + VPP + VSV + VKS) grouped = I/O
         All VCCA’S grouped = Power Group VCCA
         All VCCI’S grouped = Power Group VCCI
         All GND’s (GNDQ,GNDI,GNDA) grouped = Power Group GND
        Note: If the power groups are not internally connected via metal they are treated as
            separate power group
 MILITARY
         All IO’s (including JTAG) grouped = I/O
         All VCCA’S (VPP + VSV) grouped = Power Group VCCA
         All VCCI’S grouped = Power Group VCCI
         All GND’s (GNDQ,GNDI,GNDA, VKS) grouped = Power Group GND
        Note: Since programming pins are not specified separately per the MIL SPEC, Actel
            groups them per user configuration

All further reference to GND means the Power Group GND


ESD Characterization                                                             Date of Presentation   4
 ESD Test Sequence – TM3015.7
       Program devices with QBI design
       Pre stress functional ATE test at Actel
       Pre stress Curve trace (at Vendor site)
               If pin is an I/O, Sweep -1.5V to +1.5V with respect to GND, limiting current to 50uA.
               If pin is an I/O, Sweep -1.5V to +1.5V with respect to VCCI , limiting current to 50uA.
               If pin is an I/O, Sweep -1.5V to +1.5V with respect to VCCA, limiting current to 50uA.
               If pin is VCCI, Sweep -1.5V to +1.5V with respect to GND, limiting current to 50uA.
               If pin is VCCA, Sweep -1.5V to +1.5V with respect to GND, limiting current to 50uA
               If pin is GNDA, GNDI, & GNDQ pin, Sweep -1.5V to +1.5V with respect to V CCA
               If pin is GNDA, GNDI, & GNDQ pin, Sweep -1.5V to +1.5V with respect to V CCI
               Failure criteria is 15% shift in current
       Zap sequence
               Individual pins of I/O, V CCI & VCCA (Zap Terminal) vs. GND (Ground Terminal)
               Individual pins of I/O, GND, & V CCA (Zap Terminal) vs. VCCI (Ground Terminal)
               Individual pins of I/O, GND, & V CCI (Zap Terminal) vs. VCCA (Ground Terminal)
               Individual pins of I/O (Zap Terminal) vs. I/O (remaining pins in group) (Ground Terminal)
       Order
               Numerical starting at PIN 1
               3 +positive pulses, then curve trace, if pass then 3 –negative pulses, curve trace again
                      If fails – pin is pulled and not zapped anymore
                      Fresh device is started at the next lower zap voltage
                      Requirement is for all the 3 devices to pass every combination (no substitutions allowed)
       Back to Actel for post ATE test


ESD Characterization                                                                                  Date of Presentation   5
 ESD TM3015.7 Testing
 (HBM - MIL standard on RTSX-SU products)

 Experiment was conducted using HBM model as per MIL-STD-883F
  (Method 3015.7)
 Experiment was performed with RTSX32SU product
      Foundry – UMC
      Units used for this experiment were poly-resize processed units
 7 units were used in this experiment (Serial #’s 52714, 52712, 52715,
  52718, 52719, 52510 & 52553)
 Zap voltages ranged from 75V to 1000V
 The results of experiment are reported as follows
      200V, 150V, 100V TM3015.7 Testing with failures
      75V Testing without failures
      1000V Modified TM3015.7 Testing
 Wafer lot details and other relevant information is listed in the ensuing
  slides



ESD Characterization                                                 Date of Presentation   6
 200V TM3015.7 Test
 Serial Number 52714
                                    Product: RTSX32SU-CQ256
                                    Wafer Lot #: D19S61
                                    Design used: QBI
                                    Zap Voltage: 200V
                                    Fail criteria:
                                       Failed I-V curves (Delta shift
                                        between pre & post stress)
                                       Functional test on ATE
                        Pre-Zap         (Translates to I/O fails)
                       I-V Curve
                                    Failing Pins:
                                       GNDQ (1, 59, 128 & 189) vs.
                                        VCCI
                                    Failing Voltage Polarity:
                                     +positive

ESD Characterization                                             Date of Presentation   7
 150V TM3015.7 Test
 Serial Number 52712
                                    Product: RTSX32SU-CQ256
                                    Wafer Lot #: D19S61
                                    Design used: QBI
                                    Zap Voltage: 150V
                                    Fail criteria:
                                       Failed I-V curves (Delta shift
                                        between pre & post stress)
                        Pre-Zap        Functional test on ATE
                       I-V Curve        (Translates to I/O fails)
                                    Failing Pins:
                                       GNDQ (1, 59, 128 & 189) vs.
                                        VCCI
                                    Failing Voltage Polarity:
                                     +positive

ESD Characterization                                             Date of Presentation   8
 100V TM3015.7 Test
 Serial Number 52715
                                    Product: RTSX32SU-CQ256
                                    Wafer Lot #: D19S61
                                    Design used: QBI
                                    Zap Voltage: 100V
                                    Fail criteria:
                                       Failed I-V curves (Delta shift
                                        between pre & post stress)
                        Pre-Zap
                                       Functional test on ATE
                       I-V Curve        (Translates to I/O fails)
                                    Failing Pins:
                                       GNDQ (1, 59, 128 & 189) vs.
                                        VCCI
                                    Failing Voltage Polarity:
                                     +positive

ESD Characterization                                             Date of Presentation   9
 75V TM3015.7 Test
 Serial numbers 52718, 52719, 52510 &
Product: RTSX32SU- CQ256
Wafer Lot #: D19S61
Design used: QBI
Zap Voltage:
      75V (Serial Numbers 52718, 52719 & 52510)

Pass criteria:
      All 3 units passed I-V Curves (Delta shift between pre & post stress)
      All 3 units passed Functional test on ATE

Conclusion:
      Serial Number 52718, 52719, 52510 show ESD compliance of 75V



ESD Characterization                                            Date of Presentation   10
 1000V Modified TM3015.7 Test
 Serial number 52553
 Product: RTSX32SU-CQ256
 Wafer Lot #: D19S61
 Design used: QBI
 Zap Voltage:
      1000V (Serial Number 52553 – This unit was tested excluding all GND pins
       and it was found to have an ESD compliance of 1000V )
 Pass criteria:
      The above mentioned unit passed I-V Curves (Delta shift between pre &
       post stress)
      The above mentioned unit passed Functional test on ATE
 Conclusion:
      Testing without the GND group shows that the weakness in zaps with
       respect to the GND pins
      Next planned test will exclude only the GNDQ pins


ESD Characterization                                               Date of Presentation   11
 TM3015.7 Test Summary
 (HBM - MIL standard on RTSX-SU product)
 All pins can handle 75V or higher
 The susceptible group is the four GNDQ pins
 When all GND pins are excluded from testing, all other pins pass at 1000V


         Unit #                         52714           52712           52715         52718   52719     52510          52553
       Tested at                        200V            150V             100V         75V     75V         75V          1000V
                       I-V Curves        Fail            Fail             Fail        Pass    Pass        Pass          Pass
         Results
                       Functional        Fail            Fail             Fail        Pass    Pass        Pass          Pass
                          Pins      1, 59, 128, 189 1, 59, 128, 189 1, 59, 128, 189
  Failing Conditions    against          VCCI            VCCI             VCCI
                        Polarity     Positive Zap    Positive Zap     Positive Zap
                                                                                                                     Excluded
       Comments                                                                                                    all GND pins
                                                                                                                       at test




ESD Characterization                                                                                  Date of Presentation        12
 ESD Failure Analysis
 Post zap ATE analysis shows a functional failure on any I/O

                                                                  OE
                                                                                  IO PAD
                                                                       OUTPUT
                                                                       BUFFER
                                           FROM ARRAY




                                              ARRAY
                        OR
                                              LOGIC
                                                                          INPUT
                                                                         BUFFER
              SIGNAL IS STUCK OR TOGGLES
               INCORRECTLY (DEPENDS ON
              THE EXTENT OF DAMAGE AND
                 THE LOGIC IN BETWEEN)                CANNOT BE
                                                      PROBED BY
                                                       SILICON
                                                      EXPLORER




ESD Characterization                                                                  Date of Presentation   13
 ESD Failure Analysis–
 Input Buffer
 Simplified schematic representation of Input Buffer
 FIB pads were placed and micro-probing was done

                                     VCCI


         IO
                                    P1
                       R=200                                                                      VCCI             VCCA


                                          D
                                    PEN                                                          PO              POUT

        PAD                    EN
                                          D                   INX                                     D    OUT          D
                                                                                                                               OUTB
                                          D           D                                   D           D                 D
              ~VCCI
                                          N1a         N2a                                 N4a         NO
                                                                                                                 NOUT
                                          D           D       ESDIN       D               D
                                                                                                  GND                 GND
                                          N1b          N2b                 N3b             N2b


                                    GNDQ          GNDQ                 GNDQ            GNDQ       FIB 1                     FIB 2
                                    (3.3V)        (5.0V)               (5.0V)          (3.3V)
                                     (PCI)      (PCI / TTL)           (CMOS)          (LVTTL)
                                                                                                 LOGIC HIGH


                                                                                                                 0V                     0V
              ~VCCI

                                                                                 EN




ESD Characterization                                                                                                         Date of Presentation   14
 ESD Failure Analysis–
 Boundary Scan Register
 To confirm the Input Buffer was damaged JTAG IEEE
  1149.1 Boundary Scan Registers (BSR) can be used:
                                           Input Buffer




           Input Buffer
           Signal can be
          read back from
               here



                                          Output Buffer




ESD Characterization                              Date of Presentation   15
 RT54SX32S-CQ208E (MEC)
 Group D Failure




                          Transistor N3b




ESD Characterization                       Date of Presentation   16
 RTSX32SU-CQ256 (UMC) Poly Resize
 ESD Testing TM3015.7 100V Failure


                                     Transistor N3b




ESD Characterization                   Date of Presentation   17
 RT54SX32S-CQ208 (MEC)
 Customer Life test unit




                       Transistor N3b




ESD Characterization                    Date of Presentation   18
 RT54SX32S (MEC)
 CDM Testing 500V




                       Transistor N3b




ESD Characterization                    Date of Presentation   19
 RTSX72SU-CQ208 (UMC)
 ESD 300V Test




                       Transistor N3b




ESD Characterization                    Date of Presentation   20
 ESD Failure Analysis - Schematic
                                         VCCI


              IO
                                        P1
                           R=200                                                                         VCCI          VCCA


                                              D
                                        PEN                                                             PO           POUT

             PAD                   EN
                                              D                   INX                                        D OUT          D
                                                                                                                                 OUTB
                                              D           D                                   D              D              D
                   ~VCCI
                                              N1a         N2a                                 N4a            NO
                                                                                                                     NOUT
                                              D           D       ESDIN       D               D
                                                                                                         GNDA          GNDA
                                              N1b          N2b                 N3b             N2b


                                        GNDQ          GNDQ                 GNDQ            GNDQ
                                        (3.3V)        (5.0V)               (5.0V)          (3.3V)
                                         (PCI)      (PCI / TTL)           (CMOS)          (LVTTL)
                                                                                                      DAMAGED
                                                                                                     TRANSISTOR
                                                                                                        N3b
                   ~VCCI

                                                                                     EN



GNDQ (Q for Quiet)– isolated from GNDA and GNDI
  4 GNDQ pins per device (RT54SX32S, RT54SX72S, RTSX32SU, RTSX72SU)
  The GNDQ pins are only utilized for input buffer stage circuits

ESD Characterization                                                                                                            Date of Presentation   21
 ESD Conclusions
 Incomplete reporting of ESD results in Feb 2001 Qualification
  Summary
 ESD Sensitivity identified to > 75V
 Since the MEC and UMC I/O structure have identical fit, form and
  function, ESD performance is similar
 Same transistor in the I/O structure repeatedly identified to be
  susceptible to damage
 To confirm the Input Buffer has damage JTAG IEEE 1149.1
  Boundary Scan Registers (BSR) can be used
 Testing with different standards (MIL vs. JEDEC) show damage at
  the same location in the I/O structure
         Worst case situation is when GNDQ is zapped with respect to V CCI
         When GND grouping was excluded units pass at 1000V




ESD Characterization                                             Date of Presentation   22

								
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