6 Synchronous Sequential Logic

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					6 Synchronous Sequential Logic
6-1 Introduction

Sequential circuit, Fig.6-1
combinational circuit + memory elements (present state)

A synchronous sequential circuit
a system whose behavior can be defined
from the knowledge of its signals
at discrete instant of time

An asynchronous sequential circuit, Chap.9
a system whose behavior
depends upon the order
in which its input signals change and
can be affected at any instant of time
A synchronous sequential logic system
must employ signals
that affect the memory elements only
at discrete instants of time
by using pulses of limited duration

one pulse amplitude, logic-1
another pulse amplitude, logic-0

by a timing device(master-clock generator)
generates a periodic train of clock pulses
==> clocked sequential circuits(in this Chapter)

binary cells storing one bit of information
6-2 Flip-flops

a flip-flop circuit
can maintain a binary state indefinitely
until directed by an input signal
to switch states
(as long as power is delievered to the circuit)

Basic flip-flop circuit with NOR gates, Fig.6-2
Basic flip-flop circuit with NAND gates, Fig.6-3

two inputs, set and reset
two outputs, Q and Q’

direct-coupled RS flip-flop(or SR latch)
Q = 1 and Q’= 0; the set state(or 1-state)
Q = 0 and Q’= 1; the clear state(or 0-state)
00 01
00 10
01 01
01 10
10 01
10 10
11 01
11 10

The output of a NOR gate is 0
if any input is 1
The output of a NAND gate is 0
if any input is 0
RS flip-flop
An RS flip-flop with a clock pulse(CP) input

if CP = 0
the outputs of NAND3 and NAND4 = 1
the input 1 of the NAND1 and 2
does not change the outputs

if CP = 1 SR SS RR
00 1 1 unchanged
01 1 0 set
10 0 1 reset
11 0 0 not allowed
(b) characteristic table
given Q(t), present state
SR change Q(t+1), next state

(c) characteristic equation from table(b)
Q(t+1) = S + R’Q
SR = 0 (both S and R cannot equal to 1
the two indeterminate states
marked with X
since may result in either 0 or 1
An indeterminate condition
when CP = 1 and SR = 11
QQ’= 11
when CP = 0 and SR = 11
QQ’= 01(maintained)
if output of NAND3 -> 1 and
if output of NAND4 = 0
QQ’= 10(maintained)
if output of NAND3 = 0 and
if output of NAND4 -> 1

D flip-flop
elimination of the condition SR = 1

Fig.6-5, D flip-flop

0 01 clear
1 10 set

a gated D-latch
the D flip-flop to hold data
into its internal storage
G(for gate) : the CP input
enables the gated latch to make data entry
into the circuit

When CP = 1
The output = the data input

JK and T flip-flop
The indeterminate state of the RS flip-flop
==> complement

JK QQ’ SS RR Q(t+1)
00 01 0 0 0
00 10 0 0 1 unchanged
01 01 0 0 0
01 10 0 1 0 clear
10 01 1 0 1
10 10 0 0 1 set
11 01 1 0 1
11 10 0 1 0 complement

Characteristic equation(c)
from characteristic table(b)
The T flip-flop

0 00 unchanged
1 11 complement

Characteristic equation(c)
from characteristic table(b)

6-3 Triggering of flip-flops

the momentary change of the inputs
called a trigger
switch the state of a flip-flop
Asynchronous flip-flops(Fig.6-2 and 6-3)
require an input trigger
defined by a change of signal level
This level
must be returned to its initial value
(0 in the NOR and 1 in the NAND flip-flop)
before a second trigger is applied

Clocked flip-flops
triggered by pulse
The feedback timing problem
the feedback path
between the combinational circuit
and the memory elements
can produce instability
if the outputs of memory elements(flip-flops)
are changing while the outputs of the
combinational circuit that go to
flip-flop inputs are being sampled
by the clock pulse

can be prevented
if the outputs of flip-flops
do not start changing
until the pulse input has returned to 0
==> a flip-flop
must have a signal-propagation delay
from input to output in excess
of the pulse duration using
a physical delay unit
within a flip-flop circuit
better way
make the flip-flop sensitive
to the pulse transition
rather than the pulse duration

A clock pulse, Fig.6-8
positive pulse, negative pulse
positive edge, negative edge

The clocked flip-flops(Section 6-2)
triggered during the positive edge
of the pulse
If the other inputs of the flip-flop change
while the clock is still 1,
the flip-flop will start changing

Master-slave flip-flop
an RS master-slave flip-flop, Fig.6-9
when CP = 0 a master flip-flop disabled
a slave flip-flop enabled
Q = Y, Q’ = Y’
CP = 1 a slave flip-flop disabled
a master flip-flop enabled

Rs input changes Y and Y’

The timing relationships, Fig.6-10
The positive-edge transition of clock pulses
an RS master-slave flip-flops
with an inverter

a master-slave JK flip-flop with NAND gates, Fig.6-11
The clock input : normally 0
==> the outputs of gates 1 and 2 = 1
prevents the JK inputs
from affecting the master flip-flop

slave flip-flop
a clocked RS type
when the CP = 0
Q = Y and Q’= Y’

when the CP = 1
the JK inputs change Y and Y’
the slave flip-flop is isolated
SWAP operation
If two RS master-slave flip-flops are
connected to each other,
The states of the two flip-flops
are changed at the same negative edge.

Compare with two clocked RS flip-flops

Edge-Triggered flip-flop
the edge-triggered flip-flop
output transitions occur
at a specific level of the clock pulse
When the pulse input level > this threshold
the inputs are locked out
until the clock pulse returns to 0 and
another pulse occurs
a D-type positive-edge-triggered flip-flop

NAND gates 1 and 2 : one basic flip-flop
NAND gates 3 and 4 : another basic flip-flop

Inputs S and R of the 3rd basic flip-flop
must be maintained at logic-1
for steady state outputs
when SR = 01, Q = 1
SR = 10, Q = 0
Operation of the D-type edge-triggered flip-flop
(a) with CP = 0
D = 0,1 the outputs of NAND 2 and 3 = 1
==> SR = 11
(b) with CP = 1
When D = 0, the output of gate 4 = 1
==> the output of gate 1 = 0
When D = 1, the output of gate 4 = 0
==> the output of gate 1 = 1

disables any changes at the outputs of the flip-flop
The setup time
the D input must be maintained
at a constant value
prior to the application of the pulse
= the propagation delay through gates 4 and 1
since a change in D causes a change
in the outputs of these two gates
Assume that D does not change during the setup time and that
input CP becomes 1, Fig.6-13(b)
If D = 0 when CP becomes 1,
the S remains 1 but R changes to 0.
==. Q--> 0
If D--> 1 while CP is 1
the output of gate 4 remains at 1
since R = 0
Only when CP --> 0
the output of gate 4 changes
==> RS = 11
disables any changes of Q

The hold time
the D input must not change
after the application of the positive-going
transition of the pulse
= the propagation delay of gate 3
since R must become 0
to maintain the output of gate 4 at 1
regardless of the value of D
If D = 1 when CP = 1,
then S --> 0, but R remains at 1
==> Q --> 1

A change in D while CP = 1
does not alter SR
since the output of gate 1 remains at 1
by the S = 0
when CP --> 0,
SR --> 11 to maintain Q
In summary
when a positive-going transition
of the input clock pulse
the value of D is transferred to Q
changes in D when CP = 1,
a negative pulse transition,
when CP = 0
does not affect Q
The edge-triggered flip-flop
eliminates any feedback problems
all flip-flop in a system
should the outputs at the same time
the polarity change
by the addition of inverters
in the clock inputs

Graphic symbols
graphic symbols for flip-flops, Fig.6.14

a dynamic indicator of the clock pulse input
as the arrowhead-shape symbol
denotes that the flip-flop responds to
a positive-edge transition of the clock

a dynamic indicator with a small circle
designates a negative-edge transition
the letter symbol C, Fig.6-15(d)
denotes that the flip-flop responds
to a pulse level
(rather than a pulse transition)

Direct Inputs
direct preset and direct clear
preset and clear the flip-flop
asynchronously(without a clock pulse)
for an initial state after power is turned on

A negative-edge-triggered JK flip-flop
with direct clear
The clock-pulse input CP with a small circle
the outputs change to a negative transition
of the clock
the direct-clear input with a small circle
when 0, the flip-flop remains cleared
6-4 Analysis of clocked sequential circuit

The outputs and the next state
of a sequential circuit
a function of the inputs and the present state

Sequential circuit example Fig.6-16
A set of next-state equations for the circuit
the next state, and
the present state and
input conditions
that make the next state = 1

A(t+1) = A(t)x(t) + B(t)x(t)
B(t+1) = A’(t)x(t)

More compact form
A(t+1) = Ax + Bx
B(t+1) = A’x

The present-state value of the output
y(t) = (A(t) + B(t))x’(t)
==> y = (A+B)x’
State Table
Table 6-1,
The state table for the circuit of Fig.6-16

The present state A, B
changes to the next state A, B
with the output y
according to the input x

The next state of flip-flop A
must satisfy the state equation
A(t+1) = Ax + Bx
The next state A = 1
if input x and the present state A
both equal to 1 or
if input x and the present state B
both equal to 1

The next state of flip-flop B
must satisfy the state equation
B(t+1) = A’x

The next state B = 1
if input x = 1 and the present state A = 0

The output y
y = Ax’ + Bx’
The second form of the state table, Table 6-2

State Diagram
state diagram
a state by a circle
the transition between states
by directed lines
the each state of the flip-flop
by a binary number inside each circle

the state diagram of the sequential circuit of Fig.6-16

Flip-flop input function(input equations)
the circuit to generate the inputs to flip-flops
Example) JA = BC’x + B’Cx’
KA = B + y
Implementation, Fig.6-18
The sequential circuit of Fig.6-16
DA = Ax + Bx
DB = A’x
y = (A+B)x’

Characteristic Tables
Table 6-3, Flip-flop characteristic tables
Analysis with JK and Other Flip-flops
The next-state values of a sequential circuit
with D flip-flops
can be derived directly
from the next-sate equations
The next-state values of a sequential circuit
with JK, RS, or T flip-flops

1) Obtain the binary values
of each flip-flop input function
in terms of the present state and
input variables
2) Use the flip-flop characteristic table
to determine the next state
the flip-flop input functions
JA = B JB = x’
KA = Bx’ KB = A’x + Ax’= A?x

the state table, Table 6-4

Derive the binary values
listed under the columns
labeled flip-flop inputs

The next state of each flip-flop
evaluated from the J and K inputs and
the characteristic table
The state diagram of the sequential circuit, Fig.6-20

Mealy and Moore Models
The Mealy model
the outputs
functions of both(present states, inputs)
Fig. 6-16
output y

The Moore model
the outputs
functions of present states only
Fig. 6-19
outputs A and B
taken from the present states
synchronized with the clock
because the states are synchronized
with the clock
6-5 State Reduction and Assignment

A certain properties of sequential circuits
may be used to reduce the numebr of
gates and flip-flops

State Reduction
The reduction of the number of flip-flops
==> the state-reduction problem
( m flip-flops ==> 2m states )
Ex) Fig. 6-21, State diagram
The input sequence 01010110100
strating from the initial state a
output sequence 00000110100
state sequence aabadeffghga
Assumption) a sequential circuit
less than 7 state
As far as the input-output is concerned
two circuits are identical
if identical output sequences
for the identical input sequence
State Table, Table 6-5
For two present states
go to the same next state and
the same output
for both input combinations
States g and e : identical

Reducing the state Table, Table 6-6
Table 6-7, Reduced State Table
The same output sequence 00000110100
for the same input sequence 01010110100
although different state sequence

Figure 6-22, Reduced State Diagram

State Assignment
The state assignment problem
for the minimizing the combinational gates

Table 6-8,
Three possible Binary State Assignment
assign a unique number to a different state
140 different distinct assignments
Table 6-9,

Reduced State Table with Binary Assignment 1
no state-assignment procedures

for a minimal-cost combinational circuit

6-6 Flip-flop Excitation Tables
The characteristic table
useful for analysis and
for defining the operation of the flip-flop
specifies the next state
from the inputs and present state
The excitation table
a table of the required inputs
for a given change of state
useful for design
to know the flip-flop input conditions

Table 6-10, the excitation tables
for the 4 flip-flops

(a) RS flip-flop

Q(t) Q(t+1) SR
0 0 00
0 1 10

1 0 01

1 1 00

(b) JK flip-flop

Q(t) Q(t+1) JK
0 0 00
0 1 10
1 0 01
1 1 00
6-7 Design Procedure

The first step
a state table or a state diagram
the number of flip-flops
= the number of states

The design procedure
1) The word description
2) Obtain the state table
3) The number of States
may be reduced
by state-reduction methods
4) Assign binary values to each state
for the letter symbols of the state table
5) Determine the number of flip-flops and
Assign a letter symbols
6) Choose the type of flip-flop
7) Derive the circuit excitation and
output tables
8) Derive the circuit output functions and
the flip-flop input functions
9) Draw the logic diagram
The clocked sequential circuit
State diagram, Fig.6-23
The type of flip-flop, JK
The letter symbols to the flip-flops, A and B
The state diagram
4 states with binary values
1 input variables, x
no output variables

The state table, Table 6-11
The excitation table, Table 6-12
The block diagram of sequential circuit
with 2 JK flip-flops
Maps for combinational circuit, Fig.6-25

The logic diagram, Fig.6-26

Design with D flip-flops

For the D flip-flops
the next state = the D input
from the excitation table 6-10(c)

Table 6-13 with output y
DA = A(t+1)
DB = B(t+1)
DA(A,B,x) = ∑(2,4,5,6)
DB(A,B,x) = ∑(1,3,5,6)
y(A,B,x) = ∑(1,5)

by using map, Fig.6-27
DA = AB’ + Bx’
DB = A’x + B’x + ABx’
y = B’x

The logic diagram of the sequential circuit, Fig.6-28

Design with Unused states

Analysis of previously designed circuit
6-8 Design of counters
A counter
a sequential circuit
that goes through a prescribed sequence
of state upon the application
of input pulses

a prescribed sequence
a binary count(binary counter) or other

the state diagram of a 3-bit binary counter

Table 6-15, the excitation table
Fig.6-33, maps
logic diagram of a 3-bit binary counter

Counter with nonbinary sequence
a BCD counter from 0000 to 1001 and
returns to 0000

Table 6-16,
Excitation table for counter
with 3 JK flip-flops

The simplified functions
JA = B KA = B
JB = C KB = 1
JC = B’ KC = 1

The logic diagram of the counter, Fig.6-23(a)
The state diagram of counter, Fig.6-23(b

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