# Worst Delay Validation on Combinational Circuits Considering

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```							    Worst Delay Validation on
Combinational Circuits Considering
Process Variation and Noise Effects

Liang-Chi Chen
University of Southern California
lichen@poisson.usc.edu
http://poisson.usc.edu/~lichen
Outline
   Verify delay failure
   Gate delay models capturing simultaneous
switching
   Timing analysis for partially specified values (TA-
PSV)
   Timing-oriented ATPG
   Crosstalk ATPG for industrial circuits
   Validate worst delay on various process corners
via vector-based methods

2
Delay Failure
Combinational block

Flipflop/latch

Sampling period

   Delay failure: Delay of some input vectors through
combinational logic exceeds the sampling period
   Worst circuit delay determines maximal clock frequency
   Two approaches for finding worst circuit delay
Static timing analysis (STA)
Dynamic timing method: automated test pattern
generation (ATPG) plus timing simulation (TS)
3
Verify Delay Failure
Timing Analysis v.s. Test Generation

   Static timing analysis (STA): provides min-max timing
range for each line in circuit for both rising and falling
transition
Calculate A, T

Inputs               ... X         ...             Outputs
... Y    Z

Calculate Q

   STA overestimates timing ranges because it ignores
the dependency of specified logic and timing values.
   The idnetified timing problem is real if the excess delay
can be excited by a test vector.
   To generate such a test, timing information is needed
to be well captured by the delay models used.                4
New Delay Models
Motivation

   pin-to-pin delay may causes 30-50% error
Skew
0.40

X                                0.35
Z
Y                                0.30

Delay (ns)
0.25                                         50%
reduction
0.20
0.15
20% reduction
3/2             4/2                    0.10
X                          Y                0.05

               Z                0.00
Y          3/2                                 -0.5                   0                        0.5

3/2                                                 Skew AY-AX   (ns)
X

5
New Delay Models
Features

   Capture delay effects for simultaneous to-controlling/
to-non-controlling transitions at gate inputs
   Capture delay effects due to charge/discharge of
internal capacitances
   Handle timing ranges (can be used in STA)
   Handle partial specified input logic values to capture
tighter timing ranges - helps prune search space in
timing-oriented ATPG

6
TA-PSV
During Test Generation

   Static timing analysis provides min-max timing ranges
for all possible transitions at each line
   TA-PSV computes tighter timing ranges when some
inputs are specified
   For a completely specified vector, TA-PSV becomes
identical to timing simulation
   Key issue: for each gate, identify the worst case
corners for the terms to be calculated (A, T, or Q) for all
cases where inputs are partially specified
7
TA-PSV
Worst Case Corners for Justification

Input Value
X                    X                 X
→                    →
Y                    Y                 Y

X Z
Y
→            X Z
Y
→       X Z
Y

8
TA-PSV
Static Timing Analysis Result
0   0                 78        8 15                              16    33

0                    5
0   0                                                                   9
17          38
1                       78       8 15
0   0
7       23    9         26
2                        6
0   0
                                7
3                                                                          16    33

0   0
8                                      10
4                                   7        23       9        26    17          41

9
TA-PSV
After Line 0 is specified
16    33
0 0
0                     5   1 1

0   0                                                                  9
23        38
1                        78        8 15
0   0
7       23    9        26
2                          6
0   0
                                7
3                                                                           16    33

0   0
8                                     10
4                                     7        23       9        26   17          41

10
TA-PSV
After Line 0 and 1 are specified
16    32
0 0
0                     5   1 1

9
1 1                                                              23        36
1                        7         13
0   0
7       20    9    25
2                          6
0   0
                              7
3                                                                         16    33

0   0
8                                     10
4                                   7        20       9        25   17          38

11
TA-PSV
After All Lines are specified

0
0 0
5   1 1

9
1 1                                                 36
1                                   13
0
20
2                          6
0
                  7
3
0
8             10
4                                                        38
1 1
12
Application of TA-PSV
Test Generation on crosstalk delay

   Comparing test efficiency of ATPGs with/without TA-
PSV for similar run time.
Without TA-PSV   With TAPSV

100
ATPG efficiency

80
60
40
20
0
1    2    3     4    5    6       7   8   Circuit

13
Timing-Oriented Test Generation
Components
   A timing-oriented ATPG should contain:
Error excitation conditions at the faulty sites, and
propagation conditions at the fault-free sites
A search engine to implicitly enumerate the logic
search space
A delay model with capability to deal with timing
ranges
Timing analysis for partially specified vector (TA-
PSV) that computes more accurate timing ranges
when logic values or timing ranges at lines are
further specified
14
Timing-Oriented Test Generation
Example – Crosstalk ATPG
crosstalk site
...                             ...
...       A                 C
...       B                 D
...
...
...
the rest of the circuit

   Given a target site, crosstalk excitation criteria need to determine
required two-frame logic values and arrival/transition times at inputs of
the fault site (A and B).
   A crosstalk model is needed to determine the logic/timing information at
the outputs of site (C and D).
   Then use two-pattern ATPG and TA-PSV to determine if there exists a
test that can excite an error and propagate its effect to a primary output
with setup time violation.
   The required timing ranges at A and B imply that the crosstalk delay
model should have the capability to deal with min-max ranges.

15
Timing-Oriented Test Generation
Main Issues
   Timing requirements
Classification, conversion, and update
Propagation - timing calculation v.s. timing
implication
   Speedup the search process
Static logic implication
Pre-characterized timing propagation
Locations for logic value assignments
Justification sequence
Search scheme
   Handle new search problems
Distinghish sources of ambiguous ranges
Three-pattern test
16
Timing Requirements
Classification, Conversion, and Update
   Classification
Largest (smallest)
RF: Relative to (greater/smaller than) a fixed value
RV: Relative to a variable value
Alignment
   Conversion: All three others can be converted to RF
   Update
Revise timing requirements when logic/timing
values of a line changes

17
Propagation of Timing Requirements
Timing Calculation v.s. Implication
Static       Logic    Timing                    Timing        Logic
Timing       value    ranges                    ranges        value
Analysis                         X1
X2            AZF,S AZF,L
After                                     Z
timing                           X4             QZF,S QZF,L
calculation
QX4R,S QX4R,L
At least one input must have rising transition between QXiR,L and QXiR,L

Static        Logic   Timing                    Timing        Logic
Timing        value   ranges                    ranges        value
Analysis                          X1
X2           AZF,S AZF,L
After our                                   Z
backward                           X3
implication                        X4            QZF,S QZF,L
QX4R,L
Find all necessary directly backward implications                     18
Crosstalk ATPG for Industrial Circuits
Process Variation          Delay Model
Crosstalk Model
Defects                  All Targets                                Parasitics
Transistor/gate-level netlist

Target Identification
Fault Modeling                                                Estimation/
Validation                Extraction
Static/Dynamic Timing Analysis
Multiple Crosstalks
ATPG Engine
Layout
Fault Models              Timing Simulation

Timing Ranges             Design Errors
(Static/Dynamic)
Fault Simulation                                    Fix?              Redesign
Yes
No
Test Generation
Multi-Valued Algebra
Propagation Conditions
Fault Coverage                                     Multiple Clocks
ATPG Engine
Timing Simulation

Tests                     19
Crosstalk ATPG for Industrial Circuits
I/O
Gate Netlist with
Process   Transistor Size                  List   capacitances

Gate Delay                                Gate Delay

Preprocess:
Equations

Crosstalk                                 Crosstalk
Library                               Core ATPG
Pulse
Characterization              Pulse
Propagation                               Propagation

Equations for given                   Model parameterized
gate types &                        for capacitances &
crosstalk sites                      timing parameters

ATPG
20
1. Kernel + its I/O
ATPG - Interface                                     2. Universal data files
3. Intel developed tools
An Example Flow                 HDL netlist          4. Tools we developed in Intel
Transistor                  Standard
Layout         level netlist               cell library       Layout       Process
Circuit                                    file
Coupling   GateMaker synthesizer
Crosstalk capacitance                                 Cell size     Parasitic
Analyzer extractor          circuit flattener           finder      extractor

Victim    Coupling      HDL cell    Flattened               Cell size     Load
library    gate level               lookup                    Process
sites    parasitic                  circuit                            parasitics    parameters
data                                              table

Find large coupling                        Library                 Circuit
capacitances                                                   generator
on victim lines                      characterization
tool
Coupling nets                                               Flattened gate
coupling sizes                       Gate delay             transistor size
equations
Net name to hierarchical                            Circuit remodel
structural name mapping
Find comb. Blocks
Crosstalk target
list and coupling                   Gate netlist of comb. blocks          Crosstalk
capacitances                     with load and transistor size         tests and
Crosstalk
circuit converter Crosstalk                                                                 fault
and ATPG          equations                         ATPG                               coverage 21
Crosstalk ATPG for Industrial Circuits
Extensions
   Modeling extensions
New primitives
Interconnects
Noise and defect
   Algorithmic extensions
Multiple crosstalks
Inter-block crosstalks with multiple clocks
Inductance
   Engineering extensions
Cell remodeling

22
Crosstalk ATPG for Industrial Circuits
Experimental Results of an Older Implementation
max    #      sites      sites    sites    ATPG      CPU
identified
Ckt # net Ckt inputs identified as problem aborted efficiency time
level       as faulty     free                     (hours)
1 12856 23 1006         0%         77%     23%       77%      7.84
2    10341 29    783    0%        71%       29%      71%    13.76
3    9550   35   582     8%       75%       17%      83%    92.00
4    8407   22   740     0%       88%       12%      88%    4.28
5    5500   29   429     8%       58%       34%      66%    7.25
6    5427   26   419     1%       75%       24%      76%    29.97
7    2595   16   320     0%       87%       13%      87%    8.76
8    3023   20   206     0%       94%       6%       94%    1.85
9    2480   28   255     0%       80%       20%      80%    0.97
10    1619   25   166     6%       85%       9%       91%    1.84
11    511   17    55     5%       91%       4%       96%    0.15
Ave     -     -     -    2.5%     80.1%     17.4%    82.6%     -
23
Validate delay on process corners
   We automated the characterization process of our
delay model.
   This automation enables the modeling of multiple
process corners by running the characterization and
obtaining a delay model at each corner.
   Based on these generated models, we will be able to
run timing analysis and test generation at various
process corners and validate the timing for each corner.
   We will also understand how well the test set for
nominal process works on exciting worst delay at
various process corners, compared to the test set
generated at each corner.

24
My Expertises
   Fault diagnosis - Identify reasons of failure
 Know various fault models: stuck-at, delay, bridge, open
 Understand faulty behaviors of each models
   ATPG
 Implement timing-oriented ATPG
 ATPG for worst delay excitation
 ATPG for various faults: delay, crosstalk, bridge, open
Open is 30% of total defects
 ATPG beyond gate level (transistor level)
gate level models capture 65-84% of defects
 Extend ATPG for industrial needs: design styles, cells
   Timing characterization for resistance bridge fault
   Validation on process corners

25

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