XST Synthesis by 19lned


									XST Synthesis
FPGA Design Workshop

         After completing this module, you will be able to…

                List the synthesis options for XST
                Describe how to insert code from the
                 Language Template
                Specify various methods for entering

Presentation Name 2
 Xilinx Design Process
 • Step1: Design
        – Two design entry methods: HDL           HDL code   Schematic
          (Verilog or VHDL) or schematic
 • Step 2: Synthesize to create Netlist Synthesize
        – Translates V, VHD, SCH files into an           Netlist
          industry standard format EDIF file
 • Step 3: Implement design (netlist)            Implement
        – Translate, Map, Place & Route
                                                         BIT File
 • Step 4: Configure FPGA
        – Download BIT file into FPGA

Presentation Name 3
 XST Synthesis in Project Navigator

     Module/entity selected in Sources
      window treated as “top”
     XST-specific processes
        – Synthesize
               • View Synthesis Report
               • Analyze Hierarchy           as
               • Check Syntax             top-level
     XST-specific properties
        – Synthesis Options
        – HDL Options
        – Xilinx Specific Options

Presentation Name 5
 Device Support

           XST provides technology specific optimization for:
                     FPGAs                  CPLDs
                      –   Virtex              –   XC9500
                      –   Virtex-E            -   XC9500XL
                      –   Virtex-II           -   XC9500XV
                      –   Virtex-II Pro       -   CoolRunner
                      –   Spartan-II          -   CoolRunner-II
                      –   Spartan-IIE

Presentation Name 6
 XST Flow

                                  VHDL          Verilog

                      Synthesis                              Constraints
                      Technology Specific Optimization

                                .NGC               .LOG

                        To Implementation      Synthesis
                              Tools            Report File

Presentation Name 7
 Main Synthesis Steps


                                      HDL Parsing
                        Identification of language syntax errors

                                   HDL Synthesis
                          Macro recognition, FSM extraction,
                                  resource sharing

                              Low Level Optimization
                      Macro implementation, timing optimization,
                          LUT mapping, register replication

                                   .NGC         .LOG

Presentation Name 8
     Synthesis options
        – Global synthesis and optimization goal and

     HDL options
        – Family-specific inference and optimization

     Xilinx Specific options
        – Specific low-level implementation and
          optimization algorithms

Presentation Name 13
 XST: Synthesis Options

 • Set global synthesis,
   optimization goal, and effort
        – Optimization Goal (speed/area)
        – Optimization Effort (normal/high)
        – Synthesis Constraints File
              • Any text file
        –   Use Synthesis Constraints File
        –   Global Optimization Goal
        –   Generate RTL Schematic
        –   Write Timing Constraints
        –   Verilog 2001

Presentation Name 14
  XST: HDL Options

• Set family-specific inference
  and optimization options
     –   FSM Encoding Algorithm
     –   RAM/ROM/Multiplexer Extraction
     –   RAM/Multiplexer Style
     –   Decoder/Priority Encoder Extraction
     –   Shift Register/Logical Shifter Extraction
     –   XOR Collapsing
     –   Resource Sharing
     –   Complex Clock Enable Extraction

 Presentation Name 15
 XST: Xilinx-Specific Options

  • Set specific low-level implementation
    and optimization algorithms
         –   Add I/O Buffers
         –   Maximum Fanout
         –   Equivalent Register Removal
         –   Register Balancing
         –   Move First/Last Flip-Flop Stage
         –   Slice Packing
         –   Pack I/O Registers into IOBs

Presentation Name 16
     Language Templates

     Two methods to open templates:
        – Language Icon
        – Edit -> Language Templates
     Language Templates provide
      common templates for designs:
        – Component instantiation
        – Language templates
        – Synthesis templates

    Presentation Name 17
 Language Templates

    To use template, be sure that an HDL
     source file is already opened
    Place cursor at the location for the code
     to be entered
    In the Language Template GUI, right-
     click on the template you wish to use
    Select “Use in…”
    Be sure the appropriate file name is

Presentation Name 18
 What are Constraints?
     Writing constraints is a method of communicating your
      design and performance objectives to the synthesis tools
      and implementation tools

Presentation Name 20
   Xilinx Design Process

• Step1: Design                                    HDL code       Schematic
   – Two design entry methods: HDL(Verilog or
     VHDL) or schematic drawings
• Step 2: Synthesize to create Netlist             Synthesize        Synthesis
   – Translates V, VHD, SCH files into an industry
     standard format EDIF file                               Netlist
• Step 3: Implement design (netlist)
   – Translate, Map, Place & Route                 Implement      CONSTRAINTS
• Step 4: Configure FPGA
   – Download BIT file into FPGA                            BIT File

Presentation Name 21
 XST Constraints
 • XST will accept synthesis constraints through the
   Xilinx Constraints File (XCF)
        – Do not confuse this with the User Constraints File (UCF), which contains
          implementation constraints for the Xilinx tools

 • When using an XCF file, specify the file in the Synthesis Options

Presentation Name 22
 XST Constraints

 • To quickly enable or disable the use of a constraint file by XST,
   you can check or uncheck the Use Synthesis Constraint File menu



Presentation Name 23

 • To apply a constraint to the entire entity or module, use the following

      MODEL entity_name constraint_name = constraint_value;

 Note: If a constraint is applied to an entity or module, the constraint
       will be applied to each instance of the entity/module

 • To apply constraints to specific instances or signals within an entity or
      module, use the INST or NET keywords:

      BEGIN MODEL entity_name
           INST instance_name constraint_name = constraint_value;
           NET signal_name constraint_name = constraint_value;

Presentation Name 25
    Design Constraints

   If XST decides to push flip-flops
    to IOBs, then the following                FOE   F0E1

    cases are taken into account
            • Flip -flops controlling OBUFTs         FF1
              will be replicated


                                               FF3   FF3

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 Design Constraints
      Flip-flops having
       feedback will be
                             A                    RES
       replicated                reg     reg

                                 reg     reg



Presentation Name 28
 Design Constraints

          • If the output flip-flop belongs to a shift register and represents its last
               stage, then it will be pushed to an IOB
                 – Note: XST will not reduce the number of stages in SRL and infer additional flip-
                   flops in order to improve the clock-to-out of the slice
                 – Example: If the user has described a 16-bit shift register, then:

              RESULT Generated by XST
                                                                        SLICE         IOB=TRUE
                                                        SI                                       RES
               SI                            RES                                reg     reg
                                     reg                       14 bit
                       15 bit
             CLK                                   CLK

Presentation Name 29
  How XST Identifies Critical Paths During Timing

                  Offset_in_Before               Period           Offset_out_After

                  IPAD         logic              logic                            OPAD
                                         FF                  FF


                                   Inpad_to_Outpad                       logic     OPAD

         • Notes
                – Other synthesis tools apply frequency specification to all four regions
                – ALLCLOCKNETS (the default constraint for timing optimization) in XST represents
                  only clock-to-clock regions
                – MAX_DELAY is the constraint incorporating all four regions.

Presentation Name 30
 How XST Identifies Critical Paths During
 Timing Optimization
 • The identification of a critical path depends on the timing
   constraints and is based on the slack calculation
 • The value of the slack depends on the way the
   constraints are applied
 • As soon as all of the slacks are identified, XST will
   choose the smallest (most negative) one in order to
   identify the Critical Region
 • Let us consider the following example

Presentation Name 31
 How XST Identifies Critical Paths During
 Timing Optimization
 • Suppose we have two clocks (clk1, clk2) in the design.
   Before timing optimization their periods are estimated as:
              • clk1 : 30 ns
              • clk2 : 25 ns
 • If no value is supplied with the ALLCLOCKNETS
   constraint, XST will calculate the slack assuming the goal
   delay is 0 ns:
              • clk1 : -30 ns
              • clk2 : -25 ns
 • As a consequence, clk1 will be considered the critical
   one and XST will try to optimize this clock first

Presentation Name 32
 How XST identifies Critical Paths During
 Timing Optimization
 • Suppose a PERIOD constraint defines individual timing
   requirement for each clock: 25 ns for clk1, 15 ns for clk2.
   In this case the slack will be:
        – clk1 : -5 ns
        – clk2 : -10 ns
 • As a result, clk2 will be considered the critical one, and
   XST will try to optimize this clock first
 • The ultimate goal, in both cases, is to increase the slack
   of all paths within the Critical Region. However, the final
   results of optimization are directly affected by the types
   and values of the constraints applied

Presentation Name 33
 Understanding the Log File
 • The log file can be divided into three main parts:

                                                    HDL Compilation

                                                     HDL Analysis
                       Table of synthesis options
                                                    HDL Synthesis

                       Messages generated during       Low Level
                              synthesis                Synthesis

                                                    General Statistic
                              Final report              Table

                                                     Timing Report

Presentation Name 34
 Log File Organization

         1) Synthesis Options Summary
         2) HDL Compilation
         3) HDL Analysis
         4) HDL Synthesis
             4.1) HDL Synthesis Report
         5) Low Level Synthesis
         6) Final Report
             6.1) Device utilization summary
             6.2) TIMING REPORT
       . . .
       *                           HDL Compilation                             *
       Compiling vhdl file constant.vhd in Library my_lib.
       . . .
       *                            HDL Synthesis                              *

       Synthesizing Unit <led_dec>.
       . . .

Presentation Name 35
 Messages During Synthesis
 • The structure of this part directly reflects
   the main steps of the synthesis          • Lists files used during

                                                 • Syntax check Warnings
                              HDL Compilation      and Errors
                       ...      HDL Analysis     • Information on extracted
                                                   macros and FSMs for
    Messages generated                             each hierarchical block
                               HDL Synthesis
     during synthesis                            • Summary Table on
                                 Low Level         extracted macros for the
                                 Synthesis         entire design
                                                 • Encoding style chosen
                                                   for each FSM

                                                 • Information on register
                                                  replication and removal

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 Final Report

                       Messages generated
                        during synthesis      General
                                            Statistic Table
                          Final Report
                                            Timing Report
                                             (FPGA only)

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 Timing Report
 • XST is trying to keep its post-synthesis timing report close to the
   report generated by TRACE
 • Moreover, we have added a new table at the beginning of the
   report summarizing clock information of the design
        – List of all clocks in the design
        – How each clock is bufferized
        – How many loads each clock has

Presentation Name 38

                      XST is provided with v5.2i ISE software
                      XST provides various options for synthesizing designs
                      Language Templates allow you to re-use commonly used
                      Several methods for entering constraints

Presentation Name 39

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