Docstoc

RF CIRCUITS

Document Sample
RF CIRCUITS Powered By Docstoc
					RF   CIRCUI   TS
         Session Participants
•   Sayf Alalusi         • Ali Niknejad
•   Sam Blackman         • Manolis Terrovitis
•   Chinh Doan           • Robert Meyer
•   Brian Limketkai
•   Ian O’Donnell
•   David Sobel          • Bob Frye
•   Johan Vanderhaegen   • Andrei Vladimirescu
•   Dennis Yee
•   Robert Brodersen
    W-CDMA Transmitter/Receiver
                   Basestation Transmitter
I      DAC

                          PA
Q      DAC


             PLL                  2 GHz


                      Mobile Receiver
I     ADC

                          LNA
Q     ADC


                       PLL
              Transmitter: DAC
I       DAC

                                          PA
Q       DAC

                                       DAC specifications:
    Sam Blackman     PLL
                                         • 8 bits
                                         • 100 MHz
• Design decisions:
    – Which type of DAC to implement?
       • Binary weighted, unit element, segmented
    – Is matching going to be a problem?
    – How about SNR?
      Transmitter: LPF/Mixer
I    DAC

                                PA
Q    DAC


               PLL
                         Johan Vanderhaegen

• LPF: 2nd order Butterworth, f3db=25MHz
• Mixer: Gilbert cell
• I and Q channel are added in the current
  domain
               Wherefore 50W?
                  • Originally a trade-off for coax
                    cables
PA
                     – Maximum power handling at
         2 GHz
                       30W
                     – Minimum attenuation at 77W
                  • Is 50W still a good choice?
 LNA              • Can the antenna operate correctly
                    when its terminals are open-
Ian O’Donnell       circuited?
Sayf Alalusi      • Can we design an on-board filter
                    that has open-circuited terminals?
                          PLL
I       ADC

                                            LNA
Q       ADC


                                         PLL    Chinh Doan
• Frequency synthesizer requirements
   – Fixed frequency for direct downconversion
   – Processing gain reduces effect of reciprocal mixing
   – Correlation decreases RMS phase noise
• Relaxed requirements  low power, fully
  integrated, CMOS implementation
            Receiver: Mixer
I   ADC                • Relaxed requirements allow
                         for simpler designs consuming
                                        LNA
Q   ADC                  less power
                          – Switch sizes are kept small
          Brian Limketkai           PLL
                            thus removing the need for
                            an LO buffer
                           – Increased flicker noise due
                             to small switches in the
                             active mixer
                           – No flicker noise in passive
                             mixer
                   Receiver: ADC
I       ADC

                                                     LNA
Q       ADC


                                               PLL
      David Sobel


• Specifications: SNDR =62 dB, fNYQ=25 Ms/s
• D modulator
    – 2-1-1 multi-bit cascade for low-OSR solution
• Projected total power dissipation: <10-15 mW
• D-assisted timing recovery
  Monolithic Passive Devices

• ASITIC software
• Example circuits:
  – VCO
  – PA
                      Ali Niknejad
  Active CMOS Mixer Analysis
   Manolis Terrovitis               • Objective: Analytical Design
Switching Pair                        Methodology
(mixer core)                        • Noise: Calculate noise
               Io1 = I1-I2
                                      contribution from all internal and
         I1                  I2       external noise sources
    +          M1     M2            • Intermodulation Distortion: Fast
   VLO
                                      evaluation of the intermodulation
     -
                                      of the switching pair
                      I3 = IB+i s
                                    • Express performance in terms of
         Vin        M3                simple expressions and graphs of
                                      normalized parameters
 Transconductance
 Stage (Linear part)

				
DOCUMENT INFO
Shared By:
Categories:
Tags:
Stats:
views:9
posted:2/16/2012
language:
pages:11