# schematics

Document Sample

```					LAB 2: HIERARCHICAL COMBINATIONAL DESIGN USING MSI
MACROS
Lab Report by: Armando Sierra
Email: axs085500@utdallas.edu
Partners: Juan Sierra, Michael Garcia
Introduction:
The purpose of this lab is to learn the modular design to create large digital logic
circuits, to create and simulate basic circuit modules using verilog, and implement
hierarchical logic circuit using the prototyping board. A 2 -1 multiplexer was designed in
verilog as a building block for other circuits, then a function was implemented using
Shannon’s expansion and 2-1 multiplexers. For the last part of the experiment a binary-
to-7 segment decoder was designed and implemented using only NAND gates.

Problem Description:
The first problem required the design and implementation of a 2-1 multiplexer.
This problem was designed using the Boolean expression of a multiplexer:
Out = (~sel & a) | (sel & b);.

For the second problem the expression:
F(a,b,c,d,e) = bc’d + b(ae’ + d(e+a)’)            was implemented with four 2-1 multiplexer
using Shanno’s expansion.

F(a,b,c,d) = b( /cd + a/e + d/e/a)

= b ( /cd + /e ( a + /ad)

= b( e( /cd) + /e (a + /ad)

= b( e( /cd + c0) + /e (a +/ad)) + /b0

For the binary-to-7 segment decoder the following truth table and K-maps were used:

A    B     C    D    a    b       c   d   e   f   g
0   0    0     0    0    0    0       0   0   0   0   1
1   0    0     0    1    1    0       0   1   1   1   1
2   0    0     1    0    0    0       1   0   0   1   0
3   0    0     1    1    0    0       0   0   1   1   0
4   0    1     0    0    1    0       0   1   1   0   0
5   0    1     0    1    0    1       0   0   1   0   0
6   0    1     1    0    0    1       0   0   0   0   0
7   0    1     1    1    0    0       0   1   1   1   1
8   1    0     0    0    0    0       0   0   0   0   0
9   1    0     0    1    0    0       0   0   1   0   0
A   1   0    1    0       0   0   0   1   0   0     0
B   1   0    1    1       1   1   0   0   0   0     0
C   1   1    0    0       0   1   1   0   0   0     1
D   1   1    0    1       1   0   0   0   0   1     0
E   1   1    1    0       0   1   1   0   0   0     0
F   1   1    1    1       0   1   1   1   0   0     0

abcd 00 01 11 10
00   0  1  3  2
abcd 00 01 11 10
01   4 5   7  6
0
00      1 3 2
11   C  D F   E
01   4 5 7 6
10   8  9  B A
11   C  D  F  E
a = /a/b/cd + /ab/c/d +                           10   8  9 B   A
a/bcd + ab/cd
e = /ad + /ab/c + /b/cd

abcd 00 01 11 10
00   0  1  3  2
abcd 00 01 11 10
01   4  5 7   6                                        0
00      1 3 2
D                                              4  5
11   C     F E                                    01         7 6
8  9  B A                                         C
10                                                11      D F   E

10   8  9  B  A
b = /ab/cd + bc/d + acd + ab/c/d
f = ab/cd + /a/bd + /a/bc + /abc
abcd 00 01 11 10
00   0  1  3  2
01   4  5  7  6
abcd 00 01 11 10
11   C D   F E                                    00   0 1 3    2

10   8  9  B  A
01   4  5  7 6
c = /a/bc/d + ab/d + abc                          11   C D   F  E

10   8  9  B  A

e = /a/b/c + /abcd + ab/c/d
abcd 00 01 11 10
00   0  1 3   2

01   4 5   7 6
11   C  D  F E
10   8  9  B  A

d = /a/b/cd + /ab/c/d + bcd +
a/bc/d
To implement with only NAND gates, we used De Morgan’s law and the equivalent
NAND gates for inverters.

System analysis/ Circuit Diagram:
Problem #1:

2-1 Multiplexer

Problem #2:

F(a,b,c,d) = = b( e( /cd + c0) + /e (a +/ad)) + /b0
Problem #3:

U2 a                               U4 a
1                                  1
U1 a              2                         12                              3
1
13                                  2                                      U2 c
w                          3
9
2                           74HC10D                            74HC03D                     10             8
74HC03D                                                                                11
U3 a                                U3 b
1                                   4                                        74HC10D
3                                   6
2                                   5

74HC03D                             74HC03D

U4 b                                U4 c                                          U5 c
4                                   9                                              9
U1 b                                         6                                   8                                     8 B
4                           5                                  10                                             10
6
u                                             74HC03D                             74HC03D                                        74HC03D
5
U6 a                                U3 d
74HC03D         1                                  12
2                         12                                  11
13                                  13
U3 c
74HC10D                             74HC03D                      9
8
U1 c                                                                                 10
9                                U2 b                                U5 b
y                          8        3                                   4                                    74HC03D
10                      4                      6                                   6
5                                   5
74HC03D
74HC10D                             74HC03D

U1 d
12
z                          11
13

74HC03D
U1 a                U5 b                      U4 a
1                                            1
w                  3                                            3            U2 c
9
2                                            2
10                 8
74HC03D             74HC03D                  74HC03D        11

74HC10D

U3 a                      U3 b
1                        4
3                       6
2                        5                                                    U5 c
9
74HC03D                  74HC03D                                                      8   C
U1 b
4                                                                                       10
u                      6
5
74HC03D
U4 b                      U4 c
74HC03D         4                        9
6                       8
5                       10
U3 c
74HC03D                  74HC03D         9
8
U1 c                                                      10
9
y                      8
U5 d                      U3 d
12                       12                       74HC03D
10
11                      11
74HC03D        13                       13

74HC03D                  74HC03D

U4 d                     U5 a
U1 d          12                       1
12
11                  3
z                      11
13                       2
13
74HC03D                 74HC03D
74HC03D

U5 b                     U4 a
1
w                                                               3
U2 c
9
2
10             8
74HC03D                  74HC03D        11

74HC10D

U3 a                     U3 b
1                        4
3                       6
2                        5                                                   U5c
9
74HC03D                  74HC03D                                                  8       D
U1 b
4                                                                                      10
u                      6
5
74HC03D
U4 b                     U4 c
74HC03D         4                        9
6                       8
5                       10
U3 c
74HC03D                  74HC03D         9
8
U1 c                                                      10
9
y                      8           U5 d                     U3 d
12                       12                       74HC03D
10
11                      11
74HC03D        13                       13

74HC03D                  74HC03D

U2 b                     U5 a
U1 d          3                        1
12
4              6                       3
z                      11
5                        2
13
74HC10D                  74HC03D
74HC03D
w

U3a                          U3b
1                           4
3                    6                    U4d
2                           5                       12                                U5c
11    9
74HC03D                     74HC03D             13                                        8 E
U1b
4                                                                                                            10
6                                                                       74HC03D
u                                                                                                                                   74HC03D
5
U4b                          U4c
74HC03D                   4                           9
6                    8
5                          10
U3c
74HC03D                     74HC03D                  9
8
10
y                                                     U5d                          U3d
12                             12
74HC03D
11                   11
13                             13

74HC03D                     74HC03D

U1a                           U5a
U1d              1                               1
12
3                        3
z                                11
2                               2
13
74HC03D                         74HC03D
74HC03D

U3a                         U3 b
1                              4
U1 c                                             3                        6
9
2                              5
w                      8
10                                     74HC03D                        74HC03D
74HC03D
U2 c
U2b                         U4 a                9
3                              1
U5 c
10                     8         9
U1 b                        4                    6                        3
11                                             8 J
4                                 5                              2
10
6                                                                            74HC10D
u    5                                     74HC10D                        74HC03D
74HC03D
74HC03D
U4b                         U4 c
4                              9
6                        8
5                          10                                            U3c
9
74HC03D                        74HC03D                                          8
U5 b
10
y                                          U2a                             U3d                               74HC03D
1                              12
74HC03D                      2                    12                           11
13                              13

74HC10D                            74HC03D

U1 d                                 U6a                         U5 a
1
12                                 1
3
z                      11              2                    12
2
13                                13

74HC03D                           74HC10D                        74HC03D
U3a                     U3b
1                       4
U1c                         3                        6
9
2                       5
w                  8
10                       74HC03D                 74HC03D
74HC03D
U2c
U1a                     U4a           9
1                       1
U5c
10                8        9
U1b                         3                        3
11                                       8 G
4                   2                       2
10
6                                                     74HC10D
u    5                       74HC03D                 74HC03D
74HC03D
74HC03D
U4b                     U4c
4                       9
6                        8
5                   10                                 U3c
9
74HC03D                 74HC03D                              8
U5b
10
y                              U5d                    U3d                     74HC03D
12                  12
74HC03D                           11                      11
13                  13

74HC03D             74HC03D

U1d                 U6a                     U5a
1
12                   1
3
z                  11    2             12
2
13                  13

74HC03D             74HC10D                 74HC03D
Verilog Code:
Problem #1:

module Mul(a, b, sel, Out);
input a;
input b;
input sel;
output Out;
reg Out;

always @ (a or b or sel)
begin

Out = (~sel & a) | (sel & b);

end
endmodule

Problem #2

module lab2_2(a, b, c, d, e, G);
input a;
input b;
input c;
input d;
input e;
output G;
wire H, I, J;

Mul m1(d,1,a,I);
Mul m2(d,0,c,H);
Mul m3(I,H,e,J);
Mul m4(0,J,b,G);

endmodule
Problem #3:

module part3_edited(w,x,y,z,a,b,c,d,e,f,g,aa);

input w,x,y,z;

output a,b,c,e,d,f,g,aa;

assign aa=1;

// inverting all the inputs

nand(wn, w, w);

nand(xn, x, x);

nand(yn, y, y);

nand(zn, z, z);

//        for A

nand(t1, wn,xn,yn,z);

nand(t2, wn,x,yn,zn);

nand(t3, w,x,yn,z);

nand(t4, w,xn,y,z);

nand(a, t1,t2,t3,t4);

//        for B

nand(t5, wn,x,yn,z);

nand(t6, w,x,zn);

nand(t7, w,y,z);

nand(t8, x,y,zn);
nand(b, t5,t6,t7,t8);

//    for C

nand(t9, w,x,y);

nand(t10, wn,xn,y,zn);

nand(c, t6,t9,t10);

//    for D

nand(t11, x,y,z);

nand(t12, w,xn,y,zn);

nand(d, t1,t2,t11,t12);

//    for E

nand(t13, wn,z);

nand(t14, wn,x,yn);

nand(t15, xn,yn,z);

nand(e, t13,t14,t15);

//    for F

nand(t16, wn,xn, z);

nand(t17, wn,xn,y);

nand(t18, wn,y,z);

nand(f, t3,t16,t17,t18);
//        for G

nand(t19, wn,xn,yn);

nand(t20, wn,x,y,z);

nand(t21, w,x,yn,zn);

nand(g, t19,t20,t21);

endmodule

Test Bench:
Problem #1:

module Mul;

// Inputs
reg a;
reg b;
reg sel;

// Outputs
wire Out;

// Instantiate the Unit Under Test (UUT)
lab2num1 uut (
.a(a),
.b(b),
.sel(sel),
.Out(Out)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;
sel = 0;

// Wait 100 ns for global reset to finish
#100;

a = 0;
b = 0;
sel = 1;

// Wait 100 ns for global reset to finish
#100;

a = 0;
b = 1;
sel = 0;

// Wait 100 ns for global reset to finish
#100;

a = 0;
b = 1;
sel = 1;

// Wait 100 ns for global reset to finish
#100;

a = 1;
b = 0;
sel = 0;

// Wait 100 ns for global reset to finish
#100;

a = 1;
b = 0;
sel = 1;

// Wait 100 ns for global reset to finish
#100;

a = 1;
b = 1;
sel = 0;

// Wait 100 ns for global reset to finish
#100;

a = 1;
b = 1;
sel = 1;

// Wait 100 ns for global reset to finish
#100;

end

endmodule
Problem #2:

module lab_2_2tb_v;

// Inputs

reg a;

reg b;

reg c;

reg d;

reg e;

// Outputs

wire F;

// Instantiate the Unit Under Test (UUT)

lab2_2 uut (.a(a),.b(b),

.c(c),.d(d),.e(e), .F(F));

initial begin

// Initialize Inputs

a = 0;b = 0;c = 0;d = 0;e = 0;#100;

a = 0;b = 0;c = 0;d = 0;e = 1;#100;

a = 0;b = 0;c = 0;d = 1;e = 0;#100;

a = 0;b = 0;c = 0;d = 1;e = 1;#100;

a = 0;b = 0;c = 1;d = 0;e = 0;#100;

a = 0;b = 0;c = 1;d = 0;e = 1;#100;
a = 0;b = 0;c = 1;d = 1;e = 0;#100;

a = 0;b = 0;c = 1;d = 1;e = 1;#100;

a = 0;b = 1;c = 0;d = 0;e = 0;#100;

a = 0;b = 1;c = 0;d = 0;e = 1;#100;

a = 0;b = 1;c = 0;d = 1;e = 0;#100;

a = 0;b = 1;c = 0;d = 1;e = 1;#100;

a = 0;b = 1;c = 1;d = 0;e = 0;#100;

a = 0;b = 1;c = 1;d = 0;e = 1;#100;

a = 0;b = 1;c = 1;d = 1;e = 0;#100;

......

a = 1;b = 1;c = 0;d = 1;e = 1;#100;

a = 1;b = 1;c = 1;d = 0;e = 0;#100;

a = 1;b = 1;c = 1;d = 0;e = 1;#100;

a = 1;b = 1;c = 1;d = 1;e = 0;#100;

a = 1;b = 1;c = 1;d = 1;e = 1;#100;

end

Problem #3;

module test1;

// Inputs

reg w;

reg x;

reg y;

reg z;
// Outputs

wire a;

wire b;

wire c;

wire d;

wire e;

wire f;

wire g;

wire aa;

// Instantiate the Unit Under Test (UUT)

part3_edited uut (

.w(w),

.x(x),

.y(y),

.z(z),

.a(a),

.b(b),

.c(c),

.d(d),

.e(e),

.f(f),
.g(g),

.aa(aa)

);

initial begin

// Initialize Inputs

w = 0;

x = 0;

y = 0;

z = 0;

// Wait 100 ns for global reset to finish

#100;

w = 0;

x = 0;

y = 0;

z = 1;

// Wait 100 ns for global reset to finish

#100;w = 0;

x = 0;

y = 1;
z = 0;

// Wait 100 ns for global reset to finish

#100;w = 0;

x = 0;

y = 1;

z = 1;

// Wait 100 ns for global reset to finish

#100;w = 0;

x = 1;

y = 0;

z = 0;

// Wait 100 ns for global reset to finish

#100;w = 0;

x = 1;

y = 0;

z = 1;

// Wait 100 ns for global reset to finish

#100;w = 0;

x = 1;
y = 1;

z = 0;

// Wait 100 ns for global reset to finish

#100;w = 0;

x = 1;

y = 1;

z = 1;

// Wait 100 ns for global reset to finish

#100;w = 1;

x = 0;

y = 0;

z = 0;

// Wait 100 ns for global reset to finish

#100;w = 1;

x = 0;

y = 0;

z = 1;

// Wait 100 ns for global reset to finish

#100;w = 1;
x = 0;

y = 1;

z = 0;

// Wait 100 ns for global reset to finish

#100;w = 1;

x = 0;

y = 1;

z = 1;

// Wait 100 ns for global reset to finish

#100;w = 1;

x = 1;

y = 0;

z = 0;

// Wait 100 ns for global reset to finish

#100;w = 1;

x = 1;

y = 0;

z = 1;

// Wait 100 ns for global reset to finish
#100;w = 1;

x = 1;

y = 1;

z = 0;

// Wait 100 ns for global reset to finish

#100;

w = 1;

x = 1;

y = 1;

z = 1;

// Wait 100 ns for global reset to finish

#100;

end

endmodule
User Constraint File:
Problem #2:

NET a LOC = “P89”
NET b LOC = “P88”
NET c LOC = “P87”
NET d LOC = “P86”
NET e LOC = “P84”
NET G LOC = “P46”

Problem #3:

NET w LOC = “P89”
NET x LOC = “P88”
NET y LOC = “P87”
NET z LOC = “P86”
NET A LOC = “P46”
NET B LOC = “P45”
NET C LOC = “P44”
NET D LOC = “P43”
NET E LOC = “P42”
NET F LOC = “P41”
NET G LOC = “P37”

Wave Forms:
Problem #1:
Problem #2:

Problem #3:

Conclusion:
In the experiment, we designed and implemented a function using only a few 2-1
multiplexers, and a binary-to-7-segment decoder using only NAND gates. The functions
or our designs were tested using switches and LEDs available in the prototyping board.
The tests were consistent with the functions and output waveforms. The practice of the
experiment provided us with the necessary to create and simulate hierarchical logic
circuits using basic circuit modules.

```
DOCUMENT INFO
Shared By:
Categories:
Tags:
Stats:
 views: 11 posted: 2/15/2012 language: English pages: 23