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# num2DigitalCircuitsLabReport

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```									LAB 2: Hierarchical Combinational Design Using MSI Macros

Lab Report By: Michael Garcia
Partners: Juan Sierra Rubio, Armando Rubio
Email: mxg091000@utdallas.edu
Introduction:
In this lab, we were introduced to more complex functions using Xilinx and
modeled our design using ModelSim. We are to minimize and use Shannon’s
Expansion to implement the given design and implement the functions that were
given to us. The first problem is very simple and just asks to create a 2 by 1
multiplexer that will be used in later functions. In number two, I use this
multiplexer to Implement the required function using only four multiplexer. Finally
on number three we will create a binary-to-7 segment decoder was designed and
implemented using only NAND gates.

Problem Description:
Problem 1:

---------------------------------------------------------------------------------------
Truth Table:

Select    A       B        Z
0         0       0        0
0         0       1        0
0         1       0        1
0         1       1        1
1         0       0        0
1         0       1        1
1         1       0        0
1         1       1        1

Characteristic Table:

Select       Z
0          A
1          B
Boolean Equation:

Z = ~sel&A | sel&B;

---------------------------------------------------------------------------------------
Problem 2:

---------------------------------------------------------------------------------------
Shannon’s expansion

F(a,b,c,d) = b( /cd + a/e + d/e/a)

= b ( /cd + /e ( a + /ad)

= b( e( /cd) + /e (a + /ad)

= b( e( /cd + c0) + /e (a +/ad)) + /b0

---------------------------------------------------------------------------------------

Problem 3:

---------------------------------------------------------------------------------------

A    B     C    D    a    b       c   d   e   f   g
0   0    0     0    0    0    0       0   0   0   0   1
1   0    0     0    1    1    0       0   1   1   1   1
2   0    0     1    0    0    0       1   0   0   1   0
3   0    0     1    1    0    0       0   0   1   1   0
4   0    1     0    0    1    0       0   1   1   0   0
5   0    1     0    1    0    1       0   0   1   0   0
6   0    1     1    0    0    1       0   0   0   0   0
7   0    1     1    1    0    0       0   1   1   1   1
8   1    0     0    0    0    0       0   0   0   0   0
9   1    0     0    1    0    0       0   0   1   0   0
A   1    0     1    0    0    0       0   1   0   0   0
B   1    0     1    1    1    1       0   0   0   0   0
C   1    1     0    0    0    1       1   0   0   0   1
D   1    1     0    1    1    0       0   0   0   1   0
E   1    1     1    0    0    1       1   0   0   0   0
F   1    1     1    1    0    1       1   1   0   0   0
abcd 00 01 11 10
00   0  1  3  2
abcd 00 01 11 10
01   4 5   7  6
0
00      1 3 2
11   C  D F   E
01   4 5 7 6
10   8  9  B A
11   C  D  F  E
a = /a/b/cd + /ab/c/d +                        10   8  9 B   A
a/bcd + ab/cd
e = /ad + /ab/c + /b/cd

abcd 00 01 11 10
00   0  1  3  2
abcd 00 01 11 10
01   4  5 7   6                                     0
00      1 3 2
D                                           4  5
11   C     F E                                 01         7 6
8  9  B A                                      C
10                                             11      D F   E

10   8  9  B  A
b = /ab/cd + bc/d + acd + ab/c/d
f = ab/cd + /a/bd + /a/bc + /abc
abcd 00 01 11 10
00   0  1  3  2
01   4  5  7  6
abcd 00 01 11 10
11   C D   F E                                 00   0 1 3    2

10   8  9  B  A
01   4  5  7 6
c = /a/bc/d + ab/d + abc                       11   C D   F  E

10   8  9  B  A

e = /a/b/c + /abcd + ab/c/d
abcd 00 01 11 10
00   0  1 3   2

01   4 5   7 6
11   C  D  F E
10   8  9  B  A

d = /a/b/cd + /ab/c/d + bcd +
a/bc/d

---------------------------------------------------------------------------------------
Circuit Diagram:
Problem 1:

---------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------

Problem 2:

---------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------

EE 3120 Lab Report #2                                                             Page 5
Problem 3:

U2 a                               U4 a
1                                  1
U1 a              2                         12                              3
1
13                                  2                                      U2 c
w                             3
9
2                           74HC10D                            74HC03D                     10             8
74HC03D                                                                                11
U3 a                                U3 b
1                                   4                                        74HC10D
3                                   6
2                                   5

74HC03D                             74HC03D

U4 b                                U4 c                                          U5 c
4                                   9                                              9
U1 b                                         6                                   8                                     8 B
4                           5                                  10                                             10
6
u                                               74HC03D                             74HC03D                                        74HC03D
5
U6 a                                U3 d
74HC03D         1                                  12
2                         12                                  11
13                                  13
U3 c
74HC10D                             74HC03D                      9
8
U1 c                                                                                 10
9                                U2 b                                U5 b
y                             8        3                                   4                                    74HC03D
10                      4                      6                                   6
5                                   5
74HC03D
74HC10D                             74HC03D

U1 d
12
z                             11
13

74HC03D

EE 3120 Lab Report #2                                                                                                                          Page 6
U1 a                U5 b                      U4 a
1                                            1
w                          3                                            3            U2 c
9
2                                            2
10                 8
74HC03D             74HC03D                  74HC03D        11

74HC10D

U3 a                      U3 b
1                        4
3                       6
2                        5                                                    U5 c
9
74HC03D                  74HC03D                                                      8   C
U1 b
4                                                                                       10
u                              6
5
74HC03D
U4 b                      U4 c
74HC03D         4                        9
6                       8
5                       10
U3 c
74HC03D                  74HC03D         9
8
U1 c                                                      10
9
y                              8
U5 d                      U3 d
12                       12                       74HC03D
10
11                      11
74HC03D        13                       13

74HC03D                  74HC03D

U4 d                     U5 a
U1 d          12                       1
12
11                  3
z                              11
13                       2
13
74HC03D                 74HC03D
74HC03D

U5 b                     U4 a
1
w                                                                       3
U2 c
9
2
10             8
74HC03D                  74HC03D        11

74HC10D

U3 a                     U3 b
1                        4
3                       6
2                        5                                                   U5c
9
74HC03D                  74HC03D                                                  8       D
U1 b
4                                                                                       10
u                              6
5
74HC03D
U4 b                     U4 c
74HC03D         4                        9
6                       8
5                       10
U3 c
74HC03D                  74HC03D         9
8
U1 c                                                      10
9
y                              8           U5 d                     U3 d
12                       12                       74HC03D
10
11                      11
74HC03D        13                       13

74HC03D                  74HC03D

U2 b                     U5 a
U1 d          3                        1
12
4              6                       3
z                              11
5                        2
13
74HC10D                  74HC03D
74HC03D

EE 3120 Lab Report #2                                                                                                       Page 7
w

U3a                     U3b
1                       4
3                   6              U4d
2                       5                  12                             U5c
11    9
74HC03D                 74HC03D        13                                     8 E
U1b
4                                                                                         10
6                                                        74HC03D
u                                                                                                               74HC03D
5
U4b                     U4c
74HC03D            4                       9
6                   8
5                      10
U3c
74HC03D                 74HC03D             9
8
10
y                                             U5d                     U3d
12                         12
74HC03D
11                  11
13                         13

74HC03D                 74HC03D

U1a                      U5a
U1d          1                           1
12
3                       3
z                              11
2                           2
13
74HC03D                     74HC03D
74HC03D

---------------------------------------------------------------------------------------

EE 3120 Lab Report #2                                                                                                     Page 8
Verilog Code:
Problem 1:

---------------------------------------------------------------------------------------
module number1(a, b,sel,z);
input a;
input b;
input sel;
output z;
reg z;

always @( a or b or sel )
begin
z = (~sel & a) | (sel & b);
end
endmodule

---------------------------------------------------------------------------------------

EE 3120 Lab Report #2                                                             Page 9
Problem 2:

---------------------------------------------------------------------------------------

module lab2_2(a, b, c, d, e, G);
input a;
input b;
input c;
input d;
input e;
output G;
wire H, I, J;

number1 n1(d,1,a,I);
number1 n2(d,0,c,H);
number 1n3(I,H,e,J);
number1 n4(0,J,b,G);

endmodule

---------------------------------------------------------------------------------------

EE 3120 Lab Report #2                                                            Page 10
Problem 3:

---------------------------------------------------------------------------------------
module part3_edited(w,x,y,z,a,b,c,d,e,f,g,aa);

input w,x,y,z;

output a,b,c,e,d,f,g,aa;

assign aa=1;

// inverting all the inputs

nand(wn, w, w);

nand(xn, x, x);

nand(yn, y, y);

nand(zn, z, z);

//        for A

nand(t1, wn,xn,yn,z);

nand(t2, wn,x,yn,zn);

nand(t3, w,x,yn,z);

nand(t4, w,xn,y,z);

nand(a, t1,t2,t3,t4);

//        for B

nand(t5, wn,x,yn,z);

nand(t6, w,x,zn);

nand(t7, w,y,z);

EE 3120 Lab Report #2                                                            Page 11
nand(t8, x,y,zn);

nand(b, t5,t6,t7,t8);

//       for C

nand(t9, w,x,y);

nand(t10, wn,xn,y,zn);

nand(c, t6,t9,t10);

//       for D

nand(t11, x,y,z);

nand(t12, w,xn,y,zn);

nand(d, t1,t2,t11,t12);

//       for E

nand(t13, wn,z);

nand(t14, wn,x,yn);

nand(t15, xn,yn,z);

nand(e, t13,t14,t15);

//       for F

nand(t16, wn,xn, z);

nand(t17, wn,xn,y);

nand(t18, wn,y,z);

EE 3120 Lab Report #2             Page 12
nand(f, t3,t16,t17,t18);

//       for G

nand(t19, wn,xn,yn);

nand(t20, wn,x,y,z);

nand(t21, w,x,yn,zn);

nand(g, t19,t20,t21);

endmodule

---------------------------------------------------------------------------------------

EE 3120 Lab Report #2                                                            Page 13
Test Bench:
Problem 1:

---------------------------------------------------------------------------------------
module number1test;

// Inputs

reg a;

reg b;

reg sel;

// Outputs

wire z;

// Instantiate the Unit Under Test (UUT)

number1 uut (

.a(a),

.b(b),

.sel(sel),

.z(z)

);

initial begin

// Initialize Inputs

a = 0;

b = 0;
EE 3120 Lab Report #2                                                            Page 14
sel = 0;

// Wait 100 ns for global reset to finish

#100;

a = 0;

b = 1;

sel = 0;

// Wait 100 ns for global reset to finish

#100;

a = 1;

b = 0;

sel = 0;

// Wait 100 ns for global reset to finish

#100;

a = 1;

b = 1;

sel = 0;

EE 3120 Lab Report #2                                    Page 15
// Wait 100 ns for global reset to finish

#100;

a = 0;

b = 0;

sel = 1;

// Wait 100 ns for global reset to finish

#100;

a = 0;

b = 1;

sel = 1;

// Wait 100 ns for global reset to finish

#100;

a = 1;

b = 0;

sel = 1;

// Wait 100 ns for global reset to finish

#100;

a = 1;

EE 3120 Lab Report #2                                    Page 16
b = 1;

sel = 1;

// Wait 100 ns for global reset to finish

#100;

end

endmodule

---------------------------------------------------------------------------------------

EE 3120 Lab Report #2                                                            Page 17
Problem 2:

---------------------------------------------------------------------------------------
Problem #2:

module lab_2_2tb_v;

// Inputs

reg a;

reg b;

reg c;

reg d;

reg e;

// Outputs

wire F;

// Instantiate the Unit Under Test (UUT)

lab2_2 uut (.a(a),.b(b),

.c(c),.d(d),.e(e), .F(F));

initial begin

// Initialize Inputs

a = 0;b = 0;c = 0;d = 0;e = 0;#100;

a = 0;b = 0;c = 0;d = 0;e = 1;#100;

a = 0;b = 0;c = 0;d = 1;e = 0;#100;

a = 0;b = 0;c = 0;d = 1;e = 1;#100;

a = 0;b = 0;c = 1;d = 0;e = 0;#100;

EE 3120 Lab Report #2                                                            Page 18
a = 0;b = 0;c = 1;d = 0;e = 1;#100;

a = 0;b = 0;c = 1;d = 1;e = 0;#100;

a = 0;b = 0;c = 1;d = 1;e = 1;#100;

a = 0;b = 1;c = 0;d = 0;e = 0;#100;

a = 0;b = 1;c = 0;d = 0;e = 1;#100;

a = 0;b = 1;c = 0;d = 1;e = 0;#100;

a = 0;b = 1;c = 0;d = 1;e = 1;#100;

a = 0;b = 1;c = 1;d = 0;e = 0;#100;

a = 0;b = 1;c = 1;d = 0;e = 1;#100;

a = 0;b = 1;c = 1;d = 1;e = 0;#100;

......

a = 1;b = 1;c = 0;d = 1;e = 1;#100;

a = 1;b = 1;c = 1;d = 0;e = 0;#100;

a = 1;b = 1;c = 1;d = 0;e = 1;#100;

a = 1;b = 1;c = 1;d = 1;e = 0;#100;

a = 1;b = 1;c = 1;d = 1;e = 1;#100;

end

---------------------------------------------------------------------------------------

EE 3120 Lab Report #2                                                            Page 19
Problem 3:

---------------------------------------------------------------------------------------
module test1;

// Inputs

reg w;

reg x;

reg y;

reg z;

// Outputs

wire a;

wire b;

wire c;

wire d;

wire e;

wire f;

wire g;

wire aa;

// Instantiate the Unit Under Test (UUT)

part3_edited uut (

.w(w),

EE 3120 Lab Report #2                                                            Page 20
.x(x),

.y(y),

.z(z),

.a(a),

.b(b),

.c(c),

.d(d),

.e(e),

.f(f),

.g(g),

.aa(aa)

);

initial begin

// Initialize Inputs

w = 0;

x = 0;

y = 0;

z = 0;

// Wait 100 ns for global reset to finish

#100;

EE 3120 Lab Report #2                                     Page 21
w = 0;

x = 0;

y = 0;

z = 1;

// Wait 100 ns for global reset to finish

#100;w = 0;

x = 0;

y = 1;

z = 0;

// Wait 100 ns for global reset to finish

#100;w = 0;

x = 0;

y = 1;

z = 1;

// Wait 100 ns for global reset to finish

#100;w = 0;

x = 1;

y = 0;

z = 0;

EE 3120 Lab Report #2                                    Page 22
// Wait 100 ns for global reset to finish

#100;w = 0;

x = 1;

y = 0;

z = 1;

// Wait 100 ns for global reset to finish

#100;w = 0;

x = 1;

y = 1;

z = 0;

// Wait 100 ns for global reset to finish

#100;w = 0;

x = 1;

y = 1;

z = 1;

// Wait 100 ns for global reset to finish

#100;w = 1;

x = 0;

y = 0;

z = 0;

EE 3120 Lab Report #2                                    Page 23
// Wait 100 ns for global reset to finish

#100;w = 1;

x = 0;

y = 0;

z = 1;

// Wait 100 ns for global reset to finish

#100;w = 1;

x = 0;

y = 1;

z = 0;

// Wait 100 ns for global reset to finish

#100;w = 1;

x = 0;

y = 1;

z = 1;

// Wait 100 ns for global reset to finish

#100;w = 1;

x = 1;

y = 0;

EE 3120 Lab Report #2                                    Page 24
z = 0;

// Wait 100 ns for global reset to finish

#100;w = 1;

x = 1;

y = 0;

z = 1;

// Wait 100 ns for global reset to finish

#100;w = 1;

x = 1;

y = 1;

z = 0;

// Wait 100 ns for global reset to finish

#100;

w = 1;

x = 1;

y = 1;

z = 1;

// Wait 100 ns for global reset to finish

EE 3120 Lab Report #2                                    Page 25
#100;

end

endmodule

---------------------------------------------------------------------------------------
User Constraints File:

Problem #2:

NET a LOC = “P89”
NET b LOC = “P88”
NET c LOC = “P87”
NET d LOC = “P86”
NET e LOC = “P84”
NET G LOC = “P46”

Problem #3:

NET w LOC = “P89”
NET x LOC = “P88”
NET y LOC = “P87”
NET z LOC = “P86”
NET A LOC = “P46”
NET B LOC = “P45”
NET C LOC = “P44”
NET D LOC = “P43”
NET E LOC = “P42”
NET F LOC = “P41”
NET G LOC = “P37”

EE 3120 Lab Report #2                                                            Page 26
Waveforms/Results:
Problem 1:

---------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------
Problem 2:

---------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------

EE 3120 Lab Report #2                                                            Page 27
Problem 3:

---------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------

Conclusion:
Functions can be minimized and implemented using different tools such as
Boolean algebra, Truth Tables, Karnaugh Maps, and Verilog compilers. Implemented
designs can be entered in Xilinx as a verilog code. After the design is synthesized and
implemented in Xilinx, functional simulation of the design can be obtained as a
waveform in multisim. Before simulating in multisim, it is necessary to create a test
bench and add the necessary stimulus to the inputs. The experiment was useful for us
to gain further understanding of manual logical minimization, and also essential to learn
how to use and design in verilog compilers. We also saw how the prototype board, It
was nice since we knew the desired outputs and that was what came out. Hopefully, we
can go into deeper analysis on how these prototype boards really work and maybe
design a real clock someday.

EE 3120 Lab Report #2                                                            Page 28
EE 3120 Lab Report #2   Page 29

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