# num1DigitalCircuitsLabReprt by nguyencao0111

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```									                             Digital Circuits Lab Report #1

Combinational Logic Design Using FPGAs

Michael Garcia

E-mail - mxg091000@utdallas.edu

Lab partners (Armando and Juan Sierra Rubio)

Engr: 3120 Lab Section 102

October 3, 2009

Michael Garcia EE3120
Page 1
Experiment #1

Introduction

In this lab, we were introduced to Verilog using Xilinx and modeled our design
using ModelSim. We are to minimize the given design and implement the
functions that were given to us. Two problems are simple and modeled really easy.
The last problem will require us to build a sprinkler that will perform the desired
functions that were given.

Problem Description

*The three problems will be referred as 1, 2, and 3.*

 Approach
1.) Both parts to this problem were easily broken down using Boolean
algebra and K-Maps.
2.) This problem was slightly more difficult since we had to use Verilog
to implement the design, still we used K-Maps and Boolean algebra to
break it minimize both functions
3.) This problem required a lot thinking, we broke it down and minimized
the design with the details that were required to make it work. We
were able to implement in the end.

 Boolean Reduction, K Maps, and Truth Tables
1A.) F (a, b, c)  ac  abc  bca  ba

    F = ac + /ac + /bc + b/ca + /ba
    F = abc + a/bc +/abc + /a/bc + ab/c+a/b/c

abc       00   01     11    10
0              1     1
1        1     1     1      1

    F=a+c

Michael Garcia EE3120
Page 2
1B.) G(x,y,z) = x^y | y^z | x^ z
G = x/y + /xy + y/z +/yz + x/z +/xz
G = x/yz + x/y/z + /xyz + /xy/z + xy/z + /x/yz

xyz       00     01      11      10
0                1      1        1
1        1       1               1

G = /xz + x/y + y/z

2B.)
The second problem in the lab was the following function and truth table:

H(v,w,x,y,z) = (/v | w) & x
if y^z=0

H (v,w,x,y,z) = (v ^ w) | /x                     if y /= z
if (y^z == 0)
H = (~v|w)&x;

else if (y ^z ==1 )
H = (v^w)|x;

G:
case ({x,y,z})
000: G = 1'b0;
001: G = 1'b1;
010: G = 1'b1;
011: G = 1'b1;
100: G = 1'b0;
101: G = 1'b0;
110: G = 1'b0;
111: G = 1'b1;

X    Y     Z     G
0    0     0     0
0    0     1     1
0    1     0     1
0    1     1     1
1    0     0     0
1    0     1     0
1    1     0     0
1    1     1     1

Michael Garcia EE3120
Page 3
The third problem was to design a lawn sprinkler system with the following
specifications:

   START = 1. Start sprinkler in the morning (ON=1), if and only if it is needed.
   DRYNESS : is a 2-bit input: 00 = too dry, 01 = dry, 10 = wet, and 11 = fully watered.
   RAIN = 1. It is raining and the sprinkler should not be turned on.
   ON = 1. Turn on the sprinkler system.
   FLOW is a 2-bit output which controls the flow of water: 11 = maximum flow, 10 = medium
flow, 01 = drip, and 00 = no flow.
Start Dryness1 Dryness2 Rain         On Flow1 Flow2
0          0           0    0      0       1      1
0          0           0    1      0       1      1
0          0           1    0      0       1      0
0          0           1    1      0       1      0
0          1           0    0      0       0      1
0          1           0    1      0       0      1
0          1           1    0      0       0      0
0          1           1    1      0       0      0
1          0           0    0      1       1      1
1          0           0    1      0       1      1
1          0           1    0      1       1      0
1          0           1    1      0       1      0
1          1           0    0      1       0      1
1          1           0    1      0       0      1
1          1           1    0      1       0      0
1          1           1    1      0       0      0
Then we minimized the functions for outputs On, Flow1, and Flow2 using K-maps to
obtain the final expressions.

On          00 01 11 10                             Flow1       00 01 11 10
(s,d1,d2,r)                                         (s,d1,d2,r)
00                                                  00          1 1 1 1
01                                                  01
11            1              1                      11
10            1              1                      10          1 1 1 1

Flow2       00 01 11 10                             10           1    1
(s,d1,d2,r)
00          1 1
01            1    1
11            1    1

Michael Garcia EE3120
Page 4
On = (START) (~RAIN)   Flow2=~DRYNESS2
Flow1 = ~DRYNESS1

Michael Garcia EE3120
Page 5
Verilog Code

Verilog Code for #1A

----------------------------------------------------------------------------------------------------
module sample1(a, b, c, F);
input a;
input b;
input c;
output F;
reg F;

always@(a or b or c)
begin

F = c | a;
end

endmodule

----------------------------------------------------------------------------------------------------

Verilog Code for #1B

----------------------------------------------------------------------------------------------------
module lab1b(x, y, z, G);
input x;
input y;
input z;
output G;

reg G;
always@(x or y or z)
begin

G = (~x & z) | (x & ~y) | (y & ~z);
end

endmodule

----------------------------------------------------------------------------------------------------

Michael Garcia EE3120
Page 6
Verilog Code for #2A

----------------------------------------------------------------------------------------------------
module t_lab(v,w,x,y,z,H,G);
input v;
input w;
input x;
input y;
input z;
output H;
reg H;

always @ ( v or w or x or y or z)
begin

if (y^z == 0)
H = (~v|w)&x;

else if (y ^z ==1 )
H = (v^w)|x;

end
endmodule

----------------------------------------------------------------------------------------------------

Verilog Code for #2B

----------------------------------------------------------------------------------------------------
module t_lab(v,w,x,y,z,H,G);
input v;
input w;
input x;
input y;
input z;
output G;
reg G;

always @ ( x or y or z )
begin

case ({x,y,z})
000: G = 1'b0;
001: G = 1'b1;
010: G = 1'b1;
011: G = 1'b1;
100: G = 1'b0;
101: G = 1'b0;
110: G = 1'b0;
111: G = 1'b1;
endcase
end
endmodule

----------------------------------------------------------------------------------------------------
Michael Garcia EE3120
Page 7
Verilog Code for Sprinkler Problem

----------------------------------------------------------------------------------------------------
module prob4(start, rain, dryness, dryness2, flow, flow2, on);
input start;
input rain;
input dryness;
input dryness2;
output flow;
output flow2;
output on;

reg on;
reg flow;
reg flow2;

always @( start or dryness or rain or dryness2)
begin

on = start & ~rain;
flow = ~dryness;
flow2 = ~dryness2;
end

endmodule

----------------------------------------------------------------------------------------------------

Michael Garcia EE3120
Page 8
Test Bench

Test bench for #1A

----------------------------------------------------------------------------------------------------
module test1_v;

// Inputs
reg a;
reg b;
reg c;

// Outputs
wire F;

// Instantiate the Unit Under Test (UUT)
sample1 uut (
.a(a),
.b(b),
.c(c),
.F(F)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;
c = 0;

// Wait 100 ns for global reset to finish
#100;

a = 0;
b = 0;
c = 1;

// Wait 100 ns for global reset to finish
#100;

a = 0;
b = 1;
c = 0;

// Wait 100 ns for global reset to finish
#100;
a = 0;
b = 1;

Michael Garcia EE3120
Page 9
c = 1;

// Wait 100 ns for global reset to finish
#100;
a = 1;
b = 0;
c = 0;

// Wait 100 ns for global reset to finish
#100;
a = 1;
b = 0;
c = 1;

// Wait 100 ns for global reset to finish
#100;
a = 1;
b = 1;
c = 0;

// Wait 100 ns for global reset to finish
#100;
a = 1;
b = 1;
c = 1;

// Wait 100 ns for global reset to finish
#100;

end

endmodule

----------------------------------------------------------------------------------------------------

Michael Garcia EE3120
Page 10
Test Bench for #1B

----------------------------------------------------------------------------------------------------
module test1b_v;

// Inputs
reg x;
reg y;
reg z;

// Outputs
wire G;

// Instantiate the Unit Under Test (UUT)
lab1b uut (
.x(x),
.y(y),
.z(z),
.G(G)
);

initial begin
// Initialize Inputs
x = 0;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish
#100;
x = 0;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish
#100;
x = 0;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish
#100;
x = 0;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish
#100;

Michael Garcia EE3120
Page 11
x = 1;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish
#100;
x = 1;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish
#100;
x = 1;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish
#100;
x = 1;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish
#100;
end

endmodule

----------------------------------------------------------------------------------------------------

Michael Garcia EE3120
Page 12
Test Bench for #2A

----------------------------------------------------------------------------------------------------
module num2test;

// Inputs
reg v;
reg w;
reg x;
reg y;
reg z;

// Outputs
wire H;

// Instantiate the Unit Under Test (UUT)
t_lab uut (
.v(v),
.w(w),
.x(x),
.y(y),
.z(z),
.H(H)
);

initial begin
// Initialize Inputs
v = 0;
w = 0;
x = 0;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish
#100;

v = 0;
w = 0;
x = 0;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish2
#100;
v = 0;

Michael Garcia EE3120
Page 13
w = 0;
x = 0;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish3
#100;
v = 0;
w = 0;
x = 0;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish4
#100;
v = 0;
w = 0;
x = 1;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish5
#100;
v = 0;
w = 0;
x = 1;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish6
#100;
v = 0;
w = 0;
x = 1;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish7
#100;
v = 0;
w = 0;
x = 1;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish8
#100;
v = 0;
w = 1;
x = 0;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish9

Michael Garcia EE3120
Page 14
#100;
v = 0;
w = 1;
x = 0;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish10
#100;
v = 0;
w = 1;
x = 0;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish11
#100;
v = 0;
w = 1;
x = 0;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish12
#100;
v = 0;
w = 1;
x = 1;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish13
#100;
v = 0;
w = 1;
x = 1;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish14
#100;
v = 0;
w = 1;
x = 1;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish15
#100;
v = 0;
w = 1;
x = 1;
y = 1;
z = 1;

Michael Garcia EE3120
Page 15
// Wait 100 ns for global reset to finish16
#100;
v = 1;
w = 0;
x = 0;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish17
#100;
v = 1;
w = 0;
x = 0;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish18
#100;
v = 1;
w = 0;
x = 0;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish19
#100;
v = 1;
w = 0;
x = 0;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish20
#100;
v = 1;
w = 0;
x = 1;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish21
#100;
v = 1;
w = 0;
x = 1;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish22
#100;
v = 1;
w = 0;
x = 1;
y = 1;

Michael Garcia EE3120
Page 16
z = 0;

// Wait 100 ns for global reset to finish23
#100;
v = 1;
w = 0;
x = 1;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish24
#100;
v = 1;
w = 1;
x = 0;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish25
#100;
v = 1;
w = 1;
x = 0;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish26
#100;
v = 1;
w = 1;
x = 0;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish27
#100;
v = 1;
w = 1;
x = 0;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish28
#100;
v = 1;
w = 1;
x = 1;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish29
#100;
v = 1;
w = 1;

Michael Garcia EE3120
Page 17
x = 1;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish30
#100;
v = 1;
w = 1;
x = 1;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish31
#100;
v = 1;
w = 1;
x = 1;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish
#100;

end

endmodule

----------------------------------------------------------------------------------------------------

Michael Garcia EE3120
Page 18
Test Bench for #2B

----------------------------------------------------------------------------------------------------
module num2test;

// Inputs
reg v;
reg w;
reg x;
reg y;
reg z;

// Outputs
wire G;

// Instantiate the Unit Under Test (UUT)
t_lab uut (
.v(v),
.w(w),
.x(x),
.y(y),
.z(z),
.G(G)
);

initial begin
// Initialize Inputs
v = 0;
w = 0;
x = 0;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish
#100;

v = 0;

Michael Garcia EE3120
Page 19
w = 0;
x = 0;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish2
#100;
v = 0;
w = 0;
x = 0;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish3
#100;
v = 0;
w = 0;
x = 0;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish4
#100;
v = 0;
w = 0;
x = 1;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish5
#100;
v = 0;
w = 0;
x = 1;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish6
#100;
v = 0;
w = 0;
x = 1;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish7
#100;
v = 0;
w = 0;
x = 1;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish8
#100;

Michael Garcia EE3120
Page 20
v = 0;
w = 1;
x = 0;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish9
#100;
v = 0;
w = 1;
x = 0;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish10
#100;
v = 0;
w = 1;
x = 0;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish11
#100;
v = 0;
w = 1;
x = 0;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish12
#100;
v = 0;
w = 1;
x = 1;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish13
#100;
v = 0;
w = 1;
x = 1;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish14
#100;
v = 0;
w = 1;
x = 1;
y = 1;
z = 0;

Michael Garcia EE3120
Page 21
// Wait 100 ns for global reset to finish15
#100;
v = 0;
w = 1;
x = 1;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish16
#100;
v = 1;
w = 0;
x = 0;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish17
#100;
v = 1;
w = 0;
x = 0;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish18
#100;
v = 1;
w = 0;
x = 0;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish19
#100;
v = 1;
w = 0;
x = 0;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish20
#100;
v = 1;
w = 0;
x = 1;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish21
#100;
v = 1;
w = 0;
x = 1;
y = 0;

Michael Garcia EE3120
Page 22
z = 1;

// Wait 100 ns for global reset to finish22
#100;
v = 1;
w = 0;
x = 1;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish23
#100;
v = 1;
w = 0;
x = 1;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish24
#100;
v = 1;
w = 1;
x = 0;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish25
#100;
v = 1;
w = 1;
x = 0;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish26
#100;
v = 1;
w = 1;
x = 0;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish27
#100;
v = 1;
w = 1;
x = 0;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish28
#100;
v = 1;
w = 1;

Michael Garcia EE3120
Page 23
x = 1;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish29
#100;
v = 1;
w = 1;
x = 1;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish30
#100;
v = 1;
w = 1;
x = 1;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish31
#100;
v = 1;
w = 1;
x = 1;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish
#100;

end

endmodule

----------------------------------------------------------------------------------------------------

Michael Garcia EE3120
Page 24
Test Bench for Sprinkler Problem

----------------------------------------------------------------------------------------------------
module test5_v;

// Inputs
reg start;
reg rain;
reg dryness;
reg dryness2;

// Outputs
wire flow;
wire flow2;
wire on;

// Instantiate the Unit Under Test (UUT)
prob4 uut (
.start(start),
.rain(rain),
.dryness(dryness),
.dryness2(dryness2),
.flow(flow),
.flow2(flow2),
.on(on)
);

initial begin
// Initialize Inputs
start = 0;
rain = 0;

Michael Garcia EE3120
Page 25
dryness = 0;
dryness2 = 0;

// Wait 100 ns for global reset to finish
#100;

start = 0;
rain = 0;
dryness = 0;
dryness2 = 1;

// Wait 100 ns for global reset to finish
#100;
start = 0;
rain = 0;
dryness = 1;
dryness2 = 0;

// Wait 100 ns for global reset to finish
#100;
start = 0;
rain = 0;
dryness = 1;
dryness2 = 1;

// Wait 100 ns for global reset to finish
#100;
start = 0;
rain = 1;
dryness = 0;
dryness2 = 0;

// Wait 100 ns for global reset to finish
#100;
start = 0;
rain = 1;
dryness = 0;
dryness2 = 1;

// Wait 100 ns for global reset to finish
#100;
start = 0;
rain = 1;
dryness = 1;
dryness2 = 0;

// Wait 100 ns for global reset to finish
#100;
start = 0;
rain = 1;
dryness = 1;
dryness2 = 1;

// Wait 100 ns for global reset to finish
#100;

Michael Garcia EE3120
Page 26
start = 1;
rain = 0;
dryness = 0;
dryness2 = 0;

// Wait 100 ns for global reset to finish
#100;
start = 1;
rain = 0;
dryness = 0;
dryness2 = 1;

// Wait 100 ns for global reset to finish
#100;
start = 1;
rain = 0;
dryness = 1;
dryness2 = 0;

// Wait 100 ns for global reset to finish
#100;
start = 1;
rain = 0;
dryness = 1;
dryness2 = 1;

// Wait 100 ns for global reset to finish
#100;
start = 1;
rain = 1;
dryness = 0;
dryness2 = 0;

// Wait 100 ns for global reset to finish
#100;
start = 1;
rain = 1;
dryness = 0;
dryness2 = 1;

// Wait 100 ns for global reset to finish
#100;
start = 1;
rain = 1;
dryness = 1;
dryness2 = 0;

// Wait 100 ns for global reset to finish
#100;
start = 1;
rain = 1;
dryness = 1;
dryness2 = 1;

Michael Garcia EE3120
Page 27
// Wait 100 ns for global reset to finish
#100;

end

endmodule
;

----------------------------------------------------------------------------------------------------

Waveforms and Results

Waveforms for #1A

F (a,b,c)

Waveforms for #1B
   G(x,y,z) = x^y | y^z | x^ z

Michael Garcia EE3120
Page 28
Waveforms for #2A
   H(v,w,x,y,z) = (/v | w) & x     if y^z=0
(v ^ w) | /x   if y /= z

Michael Garcia EE3120
Page 29
Waveforms for #2B

Waveforms for controller of a Sprinkler System

Conclusion

Michael Garcia EE3120
Page 30
In this lab, we figured out and learned how to use the Verilog language and
modeled it with ModelSim. We were given several functions and asked to design
and implement them using Verilog and ModelSim. Our results did not surprise us
since we already knew what the output was going to be. In the end, I think this was
a very good tutorial since; I was not familiar with any of this. The experiment was
useful for us to gain further understanding of manual logical minimization, and
also essential to learn how to use and design in Verilog compilers. I think now I
have a better understanding of Verilog and ModelSim and I am ready for the next
assignment.

Michael Garcia EE3120
Page 31

```
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