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					LAB 1: COMBINATIONAL LOGIC DESIGN USING FPGAs

             Lab Report By: Jose Sierra

              Partner: Deepak Selvan

     E-mail adresses: Jcs107120@utdallas.edu

            Djs074000@udallas.edu
Introduction:
       Different functions were minimized and implemented using Boolean Algebra, K-
maps, and a Verilog compiler. Using these techniques, we were able to design the
controller for a lawn sprinkler system with inputs START, DRYNESS, and RAIN, and
outputs ON, and FLOW.

Problem Description:
      Parts A and B of the first two problems were manually implemented by obtaining
the minterms using Boolean algebra and minimizing with a K-map.

F (a, b, c)  ac  abc  bca  ba

F = ac + /ac + /bc + b/ca + /ba
F = abc + a/bc +/abc + /a/bc + ab/c+a/b/c

abc   00     01    11    10
 0            1    1
 1     1      1    1      1

F=a+c

G(x,y,z) = x^y | y^z | x^ z
G = x/y + /xy + y/z +/yz + x/z +/xz
G = x/yz + x/y/z + /xyz + /xy/z + xy/z + /x/yz
X     Y     Z      G
0     0     0      0
0     0     1      1
0     1     0      1
0     1     1      1
1     0     0      1
1     0     1      1
1     1     0      1
1     1     1      0
xyz       00   01     11     10
 0              1     1       1
 1        1     1             1

           G = /xz + x/y + y/z


The second problem in the lab was the following function and truth table:

H(v,w,x,y,z) = (/v | w) & x                               X   Y    Z   G
if y^z=0                                                  0   0    0   0
                                                          0   0    1   1
                                                          0   1    0   1
H (v,w,x,y,z) = (v ^ w) | /x                              0   1    1   1
if y /= z                                                 1   0    0   0
                                                          1   0    1   0
                                                          1   1    0   0
                                                          1   1    1   1

For the H function, the expressions were entered in Xilinx, and implemented. For the G
function, eight different case statements with their respective outputs were entered in
the Xilinx code.

The third problem was to design a lawn sprinkler system with the following
specifications:

          START = 1. Start sprinkler in the morning (ON=1), if and only if it is needed.
          DRYNESS : is a 2-bit input: 00 = too dry, 01 = dry, 10 = wet, and 11 = fully watered.
          RAIN = 1. It is raining and the sprinkler should not be turned on.
          ON = 1. Turn on the sprinkler system.
          FLOW is a 2-bit output which controls the flow of water: 11 = maximum flow, 10 = medium
           flow, 01 = drip, and 00 = no flow.
From this information we derived the following truth table:

      Srt             Dry1         Dry2           Rn              On         Flw1          Flw2
       0               0            0              0               0           1             1
       0               0            0              1               0           1             1
       0               0            1              0               0           1             0
       0               0            1              1               0           1             0
       0               1            0              0               0           0             1
       0               1            0              1               0           0             1
       0               1            1              0               0           0             0
       0               1            1              1               0           0             0
       1               0            0              0               1           1             1
       1               0            0              1               0           1             1
       1               0            1              0               1           1             0
       1               0            1              1               0           1             0
       1               1            0              0               1           0             1
       1               1            0              1               0           0             1
       1                  1           1   0                   1                  0               0
       1                  1           1   1                   0                  0               0


Then we minimized the functions for outputs On, Flw1, and Flw2 using K-maps to obtain
the final expressions.

On          00 01 11 10                       Flw1        00 01 11 10
(s,d1,d2,r)                                   (s,d1,d2,r)
00                                            00          1 1 1 1
01                                            01
11                1               1           11
10                1               1           10                  1    1     1       1

Flw2        00 01 11 10
(s,d1,d2,r)
00          1 1
01                1      1                     On = (START) (~RAIN)
11                1      1
                                              Flw1 = ~DRYNESS1
10                1      1
                                              Flw2 = ~DRYNESS2


Verilog Code:
Problem 1A:                                   Problem 1B:
module sample1(a, b, c, F);                   module lab1b(x, y, z, G);
 input a;                                      input x;
 input b;                                      input y;
 input c;                                      input z;
 output F;                                     output G;
        reg F;
                                                           reg G;
           always@(a or b or c)                            always@(x or y or z)
           begin                                           begin

           F = c | a;                                      G = (~x & z) | (x & ~y) | (y & ~z);
           end                                             end


endmodule                                     endmodule


                                                input v;
Problem 2A:                                     input w;
                                                input x;
module t_lab(v,w,x,y,z,H,G);                    input y;
  input z;                                             input w;
  output H;                                            input x;
           reg H;                                      input y;
                                                       input z;
          always @ ( v or w or x or y or z)            output G;
          begin                                                 reg G;

          if (y^z == 0)                                        always @ ( x or y or z )
          H = (~v|w)&x;                                        begin

          else if (y ^z ==1 )                                  case ({x,y,z})
          H = (v^w)|x;                                         000: G = 1'b0;
                                                               001: G = 1'b1;
           end                                                 010: G = 1'b1;
          endmodule                                            011: G = 1'b1;
                                                               100: G = 1'b0;
                                                               101: G = 1'b0;
                                                               110: G = 1'b0;
                                                               111: G = 1'b1;
Problem 2B:                                                    endcase
                                                               end
module t_lab(v,w,x,y,z,H,G);                                  endmodule
 input v;
Problem 3:
V_Source

module Lab1_5(start, rain, dryness, dryness2, o, flow, flow2);
      input start, rain, dryness, dryness2;
      output o,flow,flow2;
      reg o,flow,flow2;

          always@(start or dryness or rain or dryness2)
                        if(start == 1) begin
                                 if(rain == 0) begin
                                         if( (dryness == 0)&(dryness2 == 0) ) begin
                                                 o=1;
                                                 flow=1;
                                                 flow2=1;
                                         end
                                         if( (dryness == 0)&( dryness 2==1) ) begin
                                                 o=1;
                                                 flow=1;
                                                 flow2=0;
                                         end
                                         if( (dryness == 1)&( dryness 2==0) ) begin
                                                 o=1;
                                                 flow=0;
                                                 flow2=1;
                                         end
                                         if( (dryness == 1)&( dryness 2 == 1))      begin
                                                 o=0;
                                                 flow=0;
                                                 flow2=0;
                                             end
                                    end
                                    else     begin
                                             o=0;
                                             flow=0;
                                             flow2=0;
                                    end
                            end
                            else begin
                                             o=0;
                                             flow=0;
                                             flow2=0;
                            end
endmodule
Test Bench:
Problem 1A:
module test1_v;

       // Inputs
       reg a;
       reg b;
       reg c;

       // Outputs
       wire F;

       // Instantiate the Unit Under Test (UUT)
       sample1 uut (
                .a(a),
                .b(b),
                .c(c),
                .F(F)
       );

       initial begin
                 // Initialize Inputs
                 a = 0;
                 b = 0;
                 c = 0;

                   // Wait 100 ns for global reset to finish
                   #100;


                   a = 0;
                   b = 0;
                   c = 1;


                   // Wait 100 ns for global reset to finish
                   #100;

                   a = 0;
                   b = 1;
                   c = 0;


                   // Wait 100 ns for global reset to finish
                   #100;
                   a = 0;
                   b = 1;
                   c = 1;


                   // Wait 100 ns for global reset to finish
                   #100;
                   a = 1;
                   b = 0;
                   c = 0;


                   // Wait 100 ns for global reset to finish
                   #100;
                   a = 1;
                   b = 0;
                   c = 1;


                   // Wait 100 ns for global reset to finish
                   #100;
                   a = 1;
                   b = 1;
                   c = 0;


                   // Wait 100 ns for global reset to finish
                   #100;
                   a = 1;
                   b = 1;
                   c = 1;

                   // Wait 100 ns for global reset to finish
                   #100;


       end

endmodule

Problem 1B:
module test1b_v;

       // Inputs
       reg x;
reg y;
reg z;

// Outputs
wire G;

// Instantiate the Unit Under Test (UUT)
lab1b uut (
         .x(x),
         .y(y),
         .z(z),
         .G(G)
);

initial begin
          // Initialize Inputs
          x = 0;
          y = 0;
          z = 0;


         // Wait 100 ns for global reset to finish
         #100;
         x = 0;
         y = 0;
         z = 1;

         // Wait 100 ns for global reset to finish
         #100;
         x = 0;
         y = 1;
         z = 0;

         // Wait 100 ns for global reset to finish
         #100;
         x = 0;
         y = 1;
         z = 1;

         // Wait 100 ns for global reset to finish
         #100;
         x = 1;
         y = 0;
         z = 0;

         // Wait 100 ns for global reset to finish
         #100;
         x = 1;
         y = 0;
         z = 1;

         // Wait 100 ns for global reset to finish
         #100;
         x = 1;
         y = 1;
         z = 0;
                   // Wait 100 ns for global reset to finish
                   #100;
                   x = 1;
                   y = 1;
                   z = 1;

                   // Wait 100 ns for global reset to finish
                   #100;
       end

endmodule


Problem 2A:

module num2test;

       // Inputs
       reg v;
       reg w;
       reg x;
       reg y;
       reg z;

       // Outputs
       wire H;

       // Instantiate the Unit Under Test (UUT)
       t_lab uut (
                .v(v),
                .w(w),
                .x(x),
                .y(y),
                .z(z),
                .H(H)
       );

       initial begin
                 // Initialize Inputs
                 v = 0;
                 w = 0;
                 x = 0;
                 y = 0;
                 z = 0;

                   // Wait 100 ns for global reset to finish
                   #100;

                   // Add stimulus here1
                   v = 0;
                   w = 0;
                   x = 0;
                   y = 0;
z = 1;

// Wait 100 ns for global reset to finish2
#100;
v = 0;
w = 0;
x = 0;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish3
#100;
v = 0;
w = 0;
x = 0;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish4
#100;
v = 0;
w = 0;
x = 1;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish5
#100;
v = 0;
w = 0;
x = 1;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish6
#100;
v = 0;
w = 0;
x = 1;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish7
#100;
v = 0;
w = 0;
x = 1;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish8
#100;
v = 0;
w = 1;
x = 0;
y = 0;
z = 0;


// Wait 100 ns for global reset to finish9
#100;
v = 0;
w = 1;
x = 0;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish10
#100;
v = 0;
w = 1;
x = 0;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish11
#100;
v = 0;
w = 1;
x = 0;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish12
#100;
v = 0;
w = 1;
x = 1;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish13
#100;
v = 0;
w = 1;
x = 1;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish14
#100;
v = 0;
w = 1;
x = 1;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish15
#100;
v = 0;
w = 1;
x = 1;
y = 1;
z = 1;


// Wait 100 ns for global reset to finish16
#100;
v = 1;
w = 0;
x = 0;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish17
#100;
v = 1;
w = 0;
x = 0;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish18
#100;
v = 1;
w = 0;
x = 0;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish19
#100;
v = 1;
w = 0;
x = 0;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish20
#100;
v = 1;
w = 0;
x = 1;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish21
#100;
v = 1;
w = 0;
x = 1;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish22
#100;
v = 1;
w = 0;
x = 1;
y = 1;
z = 0;


// Wait 100 ns for global reset to finish23
#100;
v = 1;
w = 0;
x = 1;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish24
#100;
v = 1;
w = 1;
x = 0;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish25
#100;
v = 1;
w = 1;
x = 0;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish26
#100;
v = 1;
w = 1;
x = 0;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish27
#100;
v = 1;
w = 1;
x = 0;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish28
#100;
v = 1;
w = 1;
x = 1;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish29
#100;
v = 1;
                   w = 1;
                   x = 1;
                   y = 0;
                   z = 1;


                   // Wait 100 ns for global reset to finish30
                   #100;
                   v = 1;
                   w = 1;
                   x = 1;
                   y = 1;
                   z = 0;

                   // Wait 100 ns for global reset to finish31
                   #100;
                   v = 1;
                   w = 1;
                   x = 1;
                   y = 1;
                   z = 1;

                   // Wait 100 ns for global reset to finish
                   #100;

       end

endmodule



Problem 2B:
module num2test;

       // Inputs
       reg v;
       reg w;
       reg x;
       reg y;
       reg z;

       // Outputs
       wire G;

       // Instantiate the Unit Under Test (UUT)
       t_lab uut (
                .v(v),
                .w(w),
                .x(x),
                .y(y),
                .z(z),
                .G(G)
       );

       initial begin
// Initialize Inputs
v = 0;
w = 0;
x = 0;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish
#100;

// Add stimulus here1
v = 0;
w = 0;
x = 0;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish2
#100;
v = 0;
w = 0;
x = 0;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish3
#100;
v = 0;
w = 0;
x = 0;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish4
#100;
v = 0;
w = 0;
x = 1;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish5
#100;
v = 0;
w = 0;
x = 1;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish6
#100;
v = 0;
w = 0;
x = 1;
y = 1;
z = 0;
// Wait 100 ns for global reset to finish7
#100;
v = 0;
w = 0;
x = 1;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish8
#100;
v = 0;
w = 1;
x = 0;
y = 0;
z = 0;


// Wait 100 ns for global reset to finish9
#100;
v = 0;
w = 1;
x = 0;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish10
#100;
v = 0;
w = 1;
x = 0;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish11
#100;
v = 0;
w = 1;
x = 0;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish12
#100;
v = 0;
w = 1;
x = 1;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish13
#100;
v = 0;
w = 1;
x = 1;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish14
#100;
v = 0;
w = 1;
x = 1;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish15
#100;
v = 0;
w = 1;
x = 1;
y = 1;
z = 1;


// Wait 100 ns for global reset to finish16
#100;
v = 1;
w = 0;
x = 0;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish17
#100;
v = 1;
w = 0;
x = 0;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish18
#100;
v = 1;
w = 0;
x = 0;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish19
#100;
v = 1;
w = 0;
x = 0;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish20
#100;
v = 1;
w = 0;
x = 1;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish21
#100;
v = 1;
w = 0;
x = 1;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish22
#100;
v = 1;
w = 0;
x = 1;
y = 1;
z = 0;


// Wait 100 ns for global reset to finish23
#100;
v = 1;
w = 0;
x = 1;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish24
#100;
v = 1;
w = 1;
x = 0;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish25
#100;
v = 1;
w = 1;
x = 0;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish26
#100;
v = 1;
w = 1;
x = 0;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish27
#100;
v = 1;
w = 1;
                  x = 0;
                  y = 1;
                  z = 1;

                  // Wait 100 ns for global reset to finish28
                  #100;
                  v = 1;
                  w = 1;
                  x = 1;
                  y = 0;
                  z = 0;

                  // Wait 100 ns for global reset to finish29
                  #100;
                  v = 1;
                  w = 1;
                  x = 1;
                  y = 0;
                  z = 1;


                  // Wait 100 ns for global reset to finish30
                  #100;
                  v = 1;
                  w = 1;
                  x = 1;
                  y = 1;
                  z = 0;

                  // Wait 100 ns for global reset to finish31
                  #100;
                  v = 1;
                  w = 1;
                  x = 1;
                  y = 1;
                  z = 1;

                  // Wait 100 ns for global reset to finish
                  #100;

       end

endmodule



Problem 3:
module test5_v;

       // Inputs
       reg start;
       reg rain;
       reg dryness;
       reg dryness2;
// Outputs
wire flow;
wire flow2;
wire on;

// Instantiate the Unit Under Test (UUT)
prob4 uut (
         .start(start),
         .rain(rain),
         .dryness(dryness),
         .dryness2(dryness2),
         .flow(flow),
         .flow2(flow2),
         .on(on)
);

initial begin
          // Initialize Inputs
          start = 0;
          rain = 0;
          dryness = 0;
          dryness2 = 0;

         // Wait 100 ns for global reset to finish
         #100;

         start = 0;
         rain = 0;
         dryness = 0;
         dryness2 = 1;

         // Wait 100 ns for global reset to finish
         #100;
         start = 0;
         rain = 0;
         dryness = 1;
         dryness2 = 0;

         // Wait 100 ns for global reset to finish
         #100;
         start = 0;
         rain = 0;
         dryness = 1;
         dryness2 = 1;

         // Wait 100 ns for global reset to finish
         #100;
         start = 0;
         rain = 1;
         dryness = 0;
         dryness2 = 0;

         // Wait 100 ns for global reset to finish
         #100;
         start = 0;
         rain = 1;
dryness = 0;
dryness2 = 1;

// Wait 100 ns for global reset to finish
#100;
start = 0;
rain = 1;
dryness = 1;
dryness2 = 0;

// Wait 100 ns for global reset to finish
#100;
start = 0;
rain = 1;
dryness = 1;
dryness2 = 1;

// Wait 100 ns for global reset to finish
#100;
start = 1;
rain = 0;
dryness = 0;
dryness2 = 0;

// Wait 100 ns for global reset to finish
#100;
start = 1;
rain = 0;
dryness = 0;
dryness2 = 1;

// Wait 100 ns for global reset to finish
#100;
start = 1;
rain = 0;
dryness = 1;
dryness2 = 0;

// Wait 100 ns for global reset to finish
#100;
start = 1;
rain = 0;
dryness = 1;
dryness2 = 1;

// Wait 100 ns for global reset to finish
#100;
start = 1;
rain = 1;
dryness = 0;
dryness2 = 0;

// Wait 100 ns for global reset to finish
#100;
start = 1;
rain = 1;
            dryness = 0;
            dryness2 = 1;

            // Wait 100 ns for global reset to finish
            #100;
            start = 1;
            rain = 1;
            dryness = 1;
            dryness2 = 0;

            // Wait 100 ns for global reset to finish
            #100;
            start = 1;
            rain = 1;
            dryness = 1;
            dryness2 = 1;



            // Wait 100 ns for global reset to finish
            #100;

            // Add stimulus here

      end

endmodule
;
Waveforms/Results:
Problem 1A:
Problem 1B:




Problem 2A:




Problem 2B:
Problem 3:




Conclusion:
      Functions can be minimized and implemented using different tools such as
Boolean algebra, Truth Tables, Karnaugh Maps, and Verilog compilers. Implemented
designs can be entered in Xilinx as a verilog code. After the design is synthesized and
implemented in Xilinx, functional simulation of the design can be obtained as a
waveform in multisim. Before simulating in multisim, it is necessary to create a test
bench and add the necessary stimulus to the inputs. The experiment was useful for us
to gain further understanding of manual logical minimization, and also essential to learn
how to use and design in verilog compilers.

				
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