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LAB 3 PROBLEM _1TEST BENCH

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LAB 3 PROBLEM _1TEST BENCH Powered By Docstoc
					module test1_v;



       // Inputs

       reg d;

       reg clock;

       reg reset;



       // Outputs

       wire q;



       // Instantiate the Unit Under Test (UUT)

       lab3prob1 uut (

                 .d(d),

                 .clock(clock),

                 .reset(reset),

                 .q(q)

       );



       initial begin

      clock=1;

      forever begin

    #100 clock = ~clock;

        end

        end
initial begin

        // Initialize Inputs

        d = 0;

        reset = 0;



        // Wait 100 ns for global reset to finish

        #100;



        d = 1;

        reset = 0;

        #100;



        d = 1;

        reset = 1;

        #100;



        d = 1;

        reset = 1;

        #100;



        d = 0;

        reset = 1;

        #100;
            d = 0;

            reset = 1;

            #100;



            d = 1;

            reset = 1;

            #100;



            d = 1;

            reset = 1;

            #100;



            d = 0;

            reset = 1;

            #100;



            d = 0;

            reset = 1;

            #100;



            // Add stimulus here



      end



endmodule

				
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